Abstract: An object is to provide a display device with high productivity by reducing the number of masks and the number of steps. Another object is to provide a display device with high yield. A pixel transistor and a driver transistor are formed over a substrate having an insulating surface in the same step. A pixel electrode electrically connected to the pixel transistor is one electrode. The other electrode is supplied with a fixed potential. A region where a pair of electrodes overlap with each other is used as a capacitor. Accordingly, the number of masks and steps are reduced to provide a display device with high productivity.

Abstract: A semiconductor package includes a first semiconductor module including a plurality of semiconductor transistor chips and a first encapsulation layer disposed above the semiconductor transistor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of semiconductor driver channels and a second encapsulation layer disposed above the semiconductor driver channels. The semiconductor driver channels are configured to drive the semiconductor transistor chips.

Abstract: After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed connecting the first functional gate stack and the second functional gate stack. The ferroelectric gate interconnect structure includes a U-shaped bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure.

Abstract: A semiconductor nanocrystal characterized by having a solid state photoluminescence external quantum efficiency at a temperature of 90° C. or above that is at least 95% of the solid state photoluminescence external quantum efficiency of the semiconductor nanocrystal at 25° C. is disclosed. A semiconductor nanocrystal having a multiple LO phonon assisted charge thermal escape activation energy of at least 0.5 eV is also disclosed. A semiconductor nanocrystal capable of emitting light with a maximum peak emission at a wavelength in a range from 590 nm to 650 nm characterized by an absorption spectrum, wherein the absorption ratio of OD at 325 nm to OD at 450 nm is greater than 5.5. A semiconductor nanocrystal capable of emitting light with a maximum peak emission at a wavelength in a range from 545 nm to 590 nm characterized by an absorption spectrum, wherein the absorption ratio of OD at 325 nm to OD at 450 nm is greater than 7.

Abstract: GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.

Abstract: After forming a first functional gate stack located on a first body region of a first semiconductor material portion located in a first region of a substrate and a second functional gate stack located on a second body region of a second semiconductor material portion located in a second region of the substrate, a ferroelectric gate interconnect structure is formed connecting the first functional gate stack and the second functional gate stack. The ferroelectric gate interconnect structure includes a U-shaped bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure.

Abstract: A semiconductor device includes a high resistivity substrate, a first deep well region having a first conductive type and formed in the high resistivity substrate, a second deep well region having a second conductive type and formed on the first deep well region, a first well region having the first conductive type and formed on the second deep well region, and a transistor formed on the first well region.

Abstract: A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic bonding structure embedded therein, wherein each metallic bonding structure contains a columnar grain microstructure. Furthermore, at least one columnar grain extends across a bonding interface that is present between the metallic bonding structures. The presence of the columnar grain microstructure in the metallic bonding structures, together with at least one columnar grain microstructure extending across the bonding interface between the two bonded metallic bonding structures, can provide a 3D bonded structure having mechanical bonding strength and electrical performance enhancements.

Abstract: A method of producing a nitride fluorescent material is provided. The nitride fluorescent material undergoes less change in chromaticity under a high-temperature and high-humidity condition and are excellent in durability. The nitride fluorescent material has a composition containing: at least one element selected from the group consisting of Ca, Sr, Ba, and Mg; at least one element selected from the group consisting of Li, Na, and K; at least one element selected from the group consisting of Eu, Ce, Tb, and Mn; Al; and N. The method includes: preparing a calcined product having the composition, bringing the calcined product in contact with a fluorine-containing substance, and heat-treating the calcined product at a temperature of 200° C. or more and 500° C. or less. A light emitting device using the nitride fluorescent material is also provided.

Abstract: A multi-state MRAM device comprises N overlapping ovals defining a free ferromagnetic region. The size of the free ferromagnetic region is controlled the shape anisotropy of the configuration via at least a aspect ratio greater than 2, of the free ferromagnetic region. The free ferromagnetic region has a magnetic moment spontaneously aligned along the long axis in each oval outside the center region. A center magnetic moment has a multitude of exactly 2*N stable orientations determined by the magnetic moments in the segments of the ovals outside the center region. An embodiment is an MRAM device using tunneling junctions to achieve a multi-state memory configuration. Certain embodiments includes an electrically conducting heavy-metal layer disposed adjacent to and connected with the free ferromagnetic region. Some embodiments include a topological insulating material, such as Bi2Se3.

Abstract: This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes an interlayer dielectric layer formed over a substrate and having a contact hole; a lower contact filled in a part of the contact hole; and a variable resistance element which is disposed over and coupled to the lower contact, and has a first part filled in the contact hole and a second part disposed over the first part and protruding over the interlayer dielectric layer, wherein the first part includes a first metal which has a higher electron affinity than a component included in the second part, and an oxide of the first metal is an insulating material.

Abstract: Devices and methods for manufacturing a device are presented. The device includes a substrate and a vertical structure disposed over the substrate. The vertical structure includes one or more memory cell stacks with a dielectric layer between every two adjacent cell stacks. Each of the one or more cell stacks includes first and second first type conductors on first and second sides of the cell stack, respectively; first and second electrodes, the first electrode adjacent the first first type conductor, the second electrode adjacent the second first type conductor; and first and second memory elements, the first memory element disposed between the first first type conductor and the first electrode, the second memory element disposed between the second first type conductor and the second electrode. The device also includes a selector element disposed over the substrate and vertically traversing through a middle portion of the vertical structure.

Abstract: Heterojunction structure, also referred to as a heterostructure, of semiconductor material, in particular for a high electron mobility transistor (HEMT), includes a substrate, a stack of at least three buffer layers of a same semiconductor material with a wide bandgap EG1 based on a column-III nitride, namely an unintentionally doped first buffer layer, a second buffer layer, an unintentionally doped third buffer layer, an unintentionally doped intermediate layer, and a barrier layer arranged on the intermediate layer, said barrier layer being of a semiconductor material with a wide bandgap EG2 based on a column-III nitride; the second buffer layer has constant P+ doping throughout some or all of its thickness; and the third buffer layer includes a first region which is unintentionally doped throughout its entire thickness and at least one second region adjacent to said first region with N+ doping surrounding the first region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.

Abstract: Semiconductor structure and methods of fabrication thereof are provided which includes, for instance, providing a carbon-doped material layer within a recess of a semiconductor structure; removing, in part, carbon from the carbon-doped material layer to obtain, at least in part, a carbon-depleted region thereof, the carbon-depleted region having a modified etch property with an increased etch rate compared to an etch rate of the carbon-doped material layer; and recessing the carbon-depleted region of the carbon-doped material layer by an etching process, with the carbon-depleted region being recessed based upon, in part, the modified etch property of the carbon-depleted region.

Abstract: Methods for fabricating semiconductor devices are disclosed. An exemplary method includes forming first spacers along sidewalls of a gate structure that is disposed over a substrate and between source/drain features. A first dielectric layer is formed over the substrate and recessed to expose upper portions of the first spacers. A spacer layer is then formed over the upper portions of the first spacers. A second dielectric layer is formed over the spacer layer, and a patterned masking layer is formed over the second dielectric layer. The second dielectric layer, the spacer layer, and the first dielectric layer are patterned. For example, exposed portions of the second dielectric layer, the spacer layer (forming second spacers disposed along the upper portions of the first spacers), and the first dielectric layer are etched to form a trench exposing the gate structure and the source/drain features. The trench is filled with a conductive material.

Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A memory device, such as a selector device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. A selector device, for instance, may have a composition of selenium, arsenic, and at least one of boron, aluminum, gallium, indium, or thallium. The selector device may also be composed of germanium or silicon, or both. The relative amount of boron, aluminum, gallium, indium, or thallium may affect a threshold voltage of a memory component, and the relative amount may be selected accordingly. A memory component may, for instance have a composition that includes selenium, arsenic, and some combination of germanium, silicon, and at least one of boron, aluminum, gallium, indium, or thallium.

Abstract: A light emitting diode (LED) chip has an inclined notch. The inclined notch has at least one inclined surface. The LED chip includes a first-type doped semiconductor layer, a second-type doped semiconductor layer, a light emitting layer, a first electrode, and a second electrode. The light emitting layer is located between the first-type doped semiconductor layer and the second-type doped semiconductor layer. The inclined surface is inclined with respect to the light emitting layer. The first electrode is electrically connected to the first-type doped semiconductor layer. The second electrode is electrically connected to the second-type doped semiconductor layer. The inclined notch is disposed in the light emitting layer.

Abstract: A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive feature over the semiconductor substrate. The semiconductor device structure also includes a dielectric layer over the conductive feature and the semiconductor substrate. The semiconductor device structure further includes a conductive via surrounded by the dielectric layer and electrically connected to the conductive feature. The conductive via has a lower end and an upper end larger than the lower end, and the conductive via has a side surface curved inward.

Abstract: A memory device includes a first conductive layer, a second conductive layer, and a variable resistance layer provided between the first and second conductive layers. The variable resistance layer includes a first layer having a semiconductor or a first metal oxide containing a first metal, and a second layer provided between the first layer and the second conductive layer, having a second metal oxide containing a second metal, and having crystal grains that are not in contact with at least one of an end face of the second layer on a side of the first conductive layer or an end face of the second layer on a side of the second conductive layer.