Abstract: A method of operating a binaural hearing aid system (100) comprises an auxiliary device, wherein the hearing aids and the auxiliary device are wirelessly connected in a wireless network and wherein the power consumption is significantly reduced by having one hearing aid assuming the role of a passive slave in the wireless network. The invention further provides a binaural hearing aid system (100).

Abstract: A semiconductor memory device includes a memory cell array including a plurality of cell cores which include a first cell core corresponding to a first channel that is a normal channel and a second cell core corresponding to a second channel that is a failed channel; and an access circuit configured to perform address remapping by converting a first address of at least a first failed cell in the first cell core into a second address of at least a second cell in the second cell core, and to transmit data of at least the second cell through the first channel.

Abstract: A method is provided for testing a MEMS microphone. The MEMS microphone includes a pressure sensor positioned within a housing and a pressure input port to direct acoustic pressure from outside the housing towards the pressure sensor. An acoustic pressure source provides acoustic pressure to the MEMS microphone. A reference microphone is positioned proximal to the MEMS microphone. An output signal of the MEMS microphone and an output signal of the reference microphone are compared. A common signal component is removed from the output signal of the MEMS microphone and the output signal of the MEMS microphone is analyzed for noise due to the construction of the device and for a signal-to-noise ratio of the device. Based on the noise signal and the signal-to-noise ratio, the MEMS microphone is rejected or accepted.

Abstract: An apparatus includes a microelectromechanical system (MEMS) device having a diaphragm and a back plate; a clipping circuit coupled to the MEMS device, wherein the clipping circuit is configured to clip an output signal of the MEMS device so that the maximum signal drawn by a buffer is substantially constant over a temperature range; and an integrated circuit coupled to the clipping circuit, the integrated circuit including the buffer.

Abstract: A system for a seat in a motor vehicle that has a cabin audio system and a bass loudspeaker that is able to generate sound in the cabin. The system includes a seat active suspension system with a vibration sensor coupled to the seat, and a controller that is responsive to the vibration sensor and that outputs control signals that are provided to an electromagnetic actuator that reduces seat vibrations. The active suspension system is arranged such that it can cause a change in the audio system.

Abstract: A method and apparatus processes multi-channel audio by encoding, transmitting or recording “dry” audio tracks or “stems” in synchronous relationship with time-variable metadata controlled by a content producer and representing a desired degree and quality of diffusion. Audio tracks are compressed and transmitted in connection with synchronized metadata representing diffusion and preferably also mix and delay parameters. The separation of audio stems from diffusion metadata facilitates the customization of playback at the receiver, taking into account the characteristics of local playback environment.

Abstract: Apparatus (301) for switchable attenuation of a differential input signal from a microphone includes positive and negative non-attenuating paths (406, 410) have n- and p-type MOSFETs (421, 422, 423, 424) in back-to-back configurations; positive and negative attenuating paths (405, 409) have n- and p-type MOSFETs (415, 416, 418, 419) in back-to-back configurations in combination with resistors; a gate driver (425) applies a drive signal of one polarity (QNEG) to gates of the n-type MOSFETs in the attenuating paths and the p-type MOSFETs in the non-attenuating paths, and a drive signal of opposite polarity (QPOS) to the gates of the p-type MOSFETs in the attenuating paths and the n-type MOSFETs in the non-attenuating paths; and the state of the MOSFETs depends on the drive signals at their gates, and thus the input signal may be routed via either the non-attenuating paths or the attenuating paths by controlling the drive signals.

Abstract: A digital low pass filter for producing an output value given a target value includes a memory which stores a scaling factor, a previous output value, a previous intermediate value, and the target value; the difference between the target value and the previous output value is evaluated, and then multiplied by the scaling factor to produce an intermediate value; the previous intermediate value is multiplied by the scaling factor minus unity; the output value is evaluated by summing the previous output value, twice the intermediate value, and the previous intermediate value multiplied by the scaling factor minus unity; the output value is then stored in memory as the previous output value, and the intermediate value as the previous intermediate value, such that the filter provides a second-order response but requires fewer hardware multipliers than the direct form implementation of a second-order filter.

Abstract: Disclosed is a chip with a built-in self-test (BIST) circuit that incorporates a BIST engine that tests memories in parallel and that, prior to testing, dynamically sets the size of the address space to be swept. The BIST engine comprises an address generator that determines a superset of address space values associated with all the memories. This superset indicates the highest number of banks, the highest number of word lines per bank and the highest decode number for any of the memories. The address generator then generates test addresses and does so such that all test addresses are within a composite address space defined by the superset and, thereby within an address space that may, depending upon the memory configurations, be less than the predetermined maximum address space associated with such memories so as to reduce test time. Also disclosed is an associated BIST method for testing memories.

Abstract: The invention discloses rendering sound field signals, such as Higher-Order Ambisonics (HOA), for arbitrary loudspeaker setups, where the rendering results in highly improved localization properties and is energy preserving. This is obtained by a new type of decode matrix for sound field data, and a new way to obtain the decode matrix. In a method for rendering an audio sound field representation for arbitrary spatial loudspeaker setups, the decode matrix for the rendering to a given arrangement of target loudspeakers is obtained by steps of obtaining a number of target speakers, their positions, positions of a spherical modeling grid and a HOA order, generating a mix matrix from the positions of the modeling grid and the positions of the speakers, generating a mode matrix from the positions of the spherical modeling grid and the HOA order, calculating a first decode matrix from the mix matrix and the mode matrix, and smoothing and scaling the first decode matrix with smoothing and scaling coefficients.

Abstract: A multi-mode viterbi decoder supporting different decoding modes. The viterbi decoder comprises circuitry to output one or more data symbol values. The circuitry sets the one or more data symbol values to a first quantity of unit intervals in a first decoding mode (e.g. PAM-4). The circuitry sets the one or more data symbol values to a second quantity of unit intervals in a second decoding mode (e.g. NRZ). The second quantity of unit intervals is greater than the first quantity of unit intervals. A branch metric circuit is adapted to, in the first decoding mode, generate a set of viterbi branch metrics based on the data symbol values for the first quantity of unit intervals. The branch metric circuit is adapted to, in the second decoding mode, generate the set of viterbi branch metrics based on the data symbol values for the second quantity of unit intervals.

Abstract: A sound apparatus includes: an acceptance unit that accepts an input of an input audio signal from outside; a communication unit that accepts from a terminal apparatus first direction information indicating a first direction, the first direction being a direction in which a virtual sound source is arranged; a position information generation unit that generates virtual sound source position information based on listening position information, the first direction information and boundary information, the listening position information indicating a listening position, the boundary information indicating a boundary of a space where the virtual sound source is arranged, the virtual sound source position information indicating a position of the virtual sound source on the boundary; a signal generation unit that imparts, based on loudspeaker position information, the listening position information and the virtual sound source position information, a sound effect to the input audio signal such that a sound is heard a

Abstract: A system for multiuser, geofixed acoustic simulations using a shared soundscape built and stored on a central server, via interfaces that also allow for live and competitive modification. A central server disseminates sound events from the soundscape to individual devices carried by users, which integrate geolocation information, head orientation information, and head-related transfer functions (HRTFs) to generate user-specific audio feeds. The audio feeds may be played through headsets so that users perceive the shared, geofixed sound events.

Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

Abstract: An audio signal processing circuit includes a first obtaining unit, a regulation unit, a second obtaining unit, and a synthesis unit. The first obtaining unit obtains high-frequency audio signals from original audio signals. The regulation unit obtains a volume of the original signals and amplifies the high-frequency signals according to an amplification factor having a positive correlation with the volume of the original audio signals, to output improved audio components. The second obtaining unit obtains reference audio signals from the original audio signals. The synthesis unit synthesizes the improved audio components and the reference audio signals to output improved audio signals.

Abstract: An audio adaptor and method of communication is provided. The audio adaptor includes a first connector for connecting to a source of audio, a second connector for connecting to a telephone, a third connector for connecting to an audio output device, and an attenuator connected to the first connector and the second connector. The method involves receiving a first audio signal at a line level from the source of audio, receiving a second audio signal at the line level from a telephone, transmitting the first audio signal and the second audio signal at the line level to an audio output device, attenuating the first audio signal from the line level to a microphone level and transmitting the attenuated first audio signal.

Abstract: A memory device includes a memory component that store data. The memory device also includes a processor that receives a signal indicating that the memory component is coupled to the processor and retrieves information from the memory component. The information may include one or more algorithms capable of being performed by the memory component. The processor may then receive one or more packets associated with one or more data operations regarding the memory component. The processor may then perform the one or more data operations by using the memory component to employ the one or more algorithms.

Abstract: A nonvolatile memory system includes a nonvolatile memory device and a memory controller managing the nonvolatile memory device. The operation method includes receiving a read command and a read address from an external device, reading read data stored in memory cells connected to a selected word line of a selected memory block corresponding to the read address in response to the read command, and detecting and correcting error bits of the read data. The method includes estimating the number of error bits of unselected word lines on the basis of erase leaving times of memory cells connected to the unselected word lines of the selected memory block and the detected error bits, and performing read-reclaim operation on at least one word line among the selected word line and the unselected word lines on the basis of the estimated number of error bits.

Abstract: Example apparatus and methods combine erasure coding with data deduplication to simultaneously reduce the overall redundancy in data while increasing the redundancy of unique data. In one embodiment, an efficient representation of a data set is produced by deduplication. The efficient representation reduces duplicate data in the data set. Redundancy is then added back into the data set using erasure coding. The redundancy that is added back in adds protection to the unique data associated with the efficient representation. How much redundancy is added back in and what type of redundancy is added back in may be controlled based on an attribute (e.g., value, reference count, symbol size, number of symbols) of the unique data. Decisions concerning how much and what type of redundancy to add back in may be adapted over time based, for example, on observations of the efficiency of the overall system.

Abstract: Apparatuses and methods for error correction and detection of data from memory on a plurality of channels are described. An example apparatus includes: a first memory cell array including first input/output nodes; a second memory cell array including second input/output nodes and third input/output nodes; a first error correcting code (ECC) control circuit including fourth input/output nodes and fifth input/output nodes; and a second ECC control circuit including sixth input/output nodes coupled respectively to the third input/output nodes of the second memory cell array. The fourth input/output nodes of the first ECC control circuit are coupled respectively to the first input/output nodes of the first memory cell array. The fifth input/output nodes of the first ECC are coupled respectively to the second input/output nodes of the second memory cell array.