Abstract: Integrated circuit memory devices and operating methods map a plurality of memory cell blocks excluding defective memory cell blocks into a continuous address sequence of variable length. The memory cell blocks excluding the defective memory cell blocks, are preferably mapped to defective normal memory cell blocks, beginning at a highest memory cell block address and sequentially proceeding to lower cell block addresses, so as to generate continuous addresses for the memory cell blocks. Continuous address spaces may be provided by providing a plurality of flag blocks, a respective one of which corresponds to a respective one of the normal memory cell blocks. Each flag block contains a first indication that the corresponding normal memory cell block is nondefective, a second indication that the corresponding normal memory cell block is substituted with a redundant memory cell block, or a third indication that the corresponding normal memory cell block is substituted with another normal memory cell block.