Abstract: A processor interface assembly includes: a first interface circuit including a plurality of sub-interface circuits and configured to couple with a plurality of peripheral devices, wherein the plurality of peripheral devices is configured to occupy a pre-determined address space, and the pre-determined address space includes multiple sub-address spaces; and a controller including a register and configured to set a sub-address space occupied by at least one type of peripheral devices among the plurality of peripheral devices based on at least a portion of data stored in the register.

Abstract: A machine learning device including a general-purpose memory module interface is disclosed. The machine learning device includes a data storage circuit configured to store raw data and command data received from a host device through a memory module interface, and store machine learning data as a result of machine learning of the raw data and location data of the machine learning data, a machine learning logic circuit configured to generate the machine learning data through the machine learning of the raw data according to a pre-programmed machine learning logic, and a machine learning controller configured to read the raw data from the data storage circuit based on the command data, transmit the read raw data to the machine learning logic circuit, and write the machine learning data and the location data in the data storage circuit.

Abstract: Techniques for creating and establishing a configuration of connections between an initiator system and a target system can use whitelisted target ports, wherein the configuration only includes connections to selected whitelisted target ports. Automatic login of each initiator to all zoned and discovered target ports can be avoided where, alternatively, an on-demand or needs-based login can be performed by having each initiator only log into its whitelisted target ports. In this manner, better resource usage and scalability can be obtained using the techniques of the present disclosure. In one embodiment, the whitelisted target ports can be determined automatically using an intersection of target port lists obtained using a control path connection and using a fabric nameserver query. The configuration including the whitelisted targets can be persistently stored on the initiator system to enable restoration of the whitelisted targets across reboots and resets of the initiator system.

Abstract: A one-to-many communication circuit includes a recommended standard 232 signal transceiver, a main controller area network transceiver, and a plurality of subordinate controller area network transceivers. The recommended standard 232 signal transceiver is used to receive a control signal from a main controller and convert the control signal into a first signal conforming to the recommended standard 232 communication protocol. The main controller area network transceiver is used to convert the first signal into a second signal conforming to the controller area network communication protocol. And each of the plurality of subordinate controller area network transceivers is used to convert the second signal into a third signal conforming to the recommended standard 232 communication protocol.

Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is configured to communicate with a host over a peripheral bus. The processing circuitry is configured to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the host, and to complete the I/O transactions for the host in accordance with a network storage protocol, by running at least part of a host-side protocol stack of the network storage protocol.

Abstract: According to certain general aspects, the present embodiments relate generally to securing communication between ECUs. Example implementations can include a method of securely transmitting Controller Area Network (CAN) protocol frames via a CAN controller.

Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is to communicate with one or more hosts over a peripheral bus. The processing circuitry is to expose on the peripheral bus a peripheral-bus device that communicates with the one or more hosts using one or more instances of at least one bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the one or more hosts, and to complete the I/O transactions for the one or more hosts in accordance with one or more instances of at least one network storage protocol, by running at least part of a host-side protocol stack of the at least one network storage protocol.

Abstract: A method of a memory device, a storage system, and a memory device are provided. The method includes receiving a set of entries, where the set of entries includes a first entry from a source queue and addressed to a first destination and a second entry addressed to a second destination, determining to add a third entry associated with the first entry and addressed to the first destination to the set of entries, selecting one of the first entry and the third entry as a restock entry and the other of the first entry and the third entry as a pass-through entry, sending the restock entry to the source queue, and sending the second entry and the pass-through entry to a serial link connected to the first destination and the second destination.

Abstract: Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a data determination module configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of low data in the read data to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line; a data receiving module configured to determine whether to invert the global bus data according to the inversion flag data to output cache data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the cache data to generate output data of the DQ port; and a precharge module configured to set an initial state of the global bus to High.

Abstract: Method, apparatus and computer program product embodiments are provided for configuring the USB-C alternate mode feature of a device. The device can be configured to transmit data to both USB-C devices and legacy (non-USB) devices without requiring changes to the device's firmware. Adjusting a USB-C output setting in the device allows the USB-C alternate mode to be switched on or off which enables the device to be updated based on the USB-C capability of other devices connected to the device.

Abstract: A memory system includes a memory device and a controller suitable for controlling the memory device based on read counts for a plurality of pages of the memory device, wherein the controller counts at least one of the read counts in response to a read request, determines whether there is a page whose read count is initialized at every check-pointing period to generate a determination result, and controls the memory device to update the read counts based on the determination result.

Abstract: Various implementations described herein relate to systems and methods for a solid state drive (SSD) that includes a first controller and a NAND package. The NAND package includes a plurality of dies grouped into a plurality of subsets. The NAND package includes a second controller operatively coupled to each of the plurality of subsets via a corresponding one of a plurality of parallel mode channels. The first controller is operatively coupled to the NAND package via a serial link.

Abstract: An information handling system may include a processor, a display device communicatively coupled to the processor, and a basic input/output system (BIOS) communicatively coupled to the processor and configured to cause the processor to, during a pre-boot environment of the information handling system, collect contextual information regarding the information handling system, based on the contextual information, determine whether to enable soft keyboard functionality, and responsive to a determination to enable soft keyboard functionality, cause display of soft keyboard functionality to the display device.

Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is configured to communicate with a host over a peripheral bus. The processing circuitry is configured to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the host, and to complete the I/O transactions for the host in accordance with a network storage protocol, by running at least part of a host-side protocol stack of the network storage protocol.

Abstract: An authentication and information system for use in a surgical stapling system includes a microprocessor configured to demultiplex data from a plurality of components in the surgical system. The authentication and information system can include one wire chips and a coupling assembly with a communication connection.

Abstract: A data bus is determined to be in a write mode. Whether a number of memory queues that identify at least one write operation satisfies a threshold criterion is determined. The memory queues include identifiers of one or more write operations and identifiers of one or more read operations. Responsive to determining that the number of memory queues satisfies the threshold criterion, a write operation from the memory queues is transmitted over the data bus.

Abstract: A far-end data migration device and method based on a FPGA cloud platform. The device includes a server, a switch, and a plurality of FPGA acceleration cards. The server transmits data to be accelerated to the FPGA acceleration cards by means of the switch. The FPGA acceleration cards are configured to perform a primary and/or secondary acceleration on the data, and are configured to migrate the accelerated data. The method includes: transmitting data to be accelerated to a FPGA acceleration card from a server by means of a switch; performing, by the FPGA acceleration card, a primary and/or secondary acceleration on the data to be accelerated; and migrating, by the FPGA acceleration card, the accelerated data.

Abstract: A computing device includes: a housing defining an exterior of the computing device; a controller supported within the housing; a first communication port disposed on the exterior; a second communication port disposed on the exterior; a port-sharing subsystem supported within the housing, having (i) a first state to connect the controller with the first communication port, exclusive of the second communication port, and (ii) a second state to connect the controller with the first communication port and the second communication port; the controller configured to: detect engagement of an external device with the first communication port; obtain connection parameters from the external device; based on the connection parameters, set the port-sharing subsystem in either the first state or the second state; and establish a connection to the external device via the port-sharing subsystem and the first communication port.

Abstract: A device includes a memory, a plurality of registers, a multiplexer/demultiplexer circuit, and a controller circuit. The memory stores a plurality of pages of pointers and a table of commands. The plurality of registers store information about a plurality of target devices. The multiplexer/demultiplexer circuit selects (i) information from a register of the plurality of registers based on a request received from a target device of the plurality of target devices, (ii) a page from the plurality of pages based on the selected information, and (iii) a pointer from the selected page based on the selected information. The controller circuit executes a command from the table of commands based on the selected pointer.

Abstract: Pairing of an external device using a random user action is disclosed herein. An example method includes restricting the external device from accessing a resource. A user input receivable from the external device is identified based on a type of the external device, the user input not included in a list of previously generated user actions. In response to receipt of the user input from the external device within a threshold time period, the external device is authorized to access the resource.