Abstract: A load device is coupled to an electronic device. The load device include a load, an input interface, an output interface, a detecting module, and a switch module. The detecting module can determine if a parameter of an input power from the input interface is greater than a predefined parameter. The switch module is connected to the input interface, the load and the output interface. The switch module being configured to switch off the input power to the load and the output interface when the parameter of the input power from the electronic device is not greater than the predefined parameter.

Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

Abstract: A method and system for regulation and control of a multi-core CPU includes receiving an operating command associated with regulation and control of the multi-core CPU, responding to the operating command, and performing regulation and control on the CPU cores of the multi-core CPU via a bottom layer core interface according to a preset CPU regulation and control mode. Thereby, a working state of every CPU core of a multi-core CPU is regulated and controlled, processing capability of the multi-core CPU is improved, and energy and electric power are saved.

Abstract: Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.

Abstract: Embodiments relate to reestablishing synchronization across multiple channels in a memory system. One aspect is a computer implemented method that includes receiving an out-of-synchronization indication associated with at least one of a plurality of channels in the memory system. A memory control unit in communication with the channels performs a first stage of reestablishing synchronization that includes selectively stopping new traffic on the plurality of channels, waiting for a first time period to expire, resuming traffic on the plurality of channels based on the first time period expiring, and verifying that synchronization is reestablished for a second time period.

Abstract: A smart card may include data storage and transmission circuitry, a plurality of voltage controllers to supply operational power to card circuitry, a plurality of oscillators to supply an internal clock for the card, and power management circuitry. The power management circuitry may be configured to shut down the oscillators and at least one, but not all, voltage controllers during a period after a data transmission is completed.

Abstract: Embodiments of the virtual machine power metering system and method measure the power consumption of individual virtual machines. Power meter measurements for a physical host server are converted into individual virtual machine power meters that measure the power consumption of each individual virtual machine residing on the host server. The virtual machine power consumption is computed by generating a power model using the total power consumption of the host server and resource utilization for a virtual machine. Optimal power model coefficients are computed using the power model. The energy used by the virtual machine is computed using one of two embodiments. Embodiments of the system and method also can be used to obtain the power consumption for a specific activity (such as a service, request, or search query). In addition, the virtual machine power metering can be used for virtual machine power capping to allow power oversubscription in virtualized environments.

Abstract: Aspects of the subject technology relate to executing a boot sequence from a recovery image. A determination of a validity of one or more keyblocks is made. A determination of a first version identifier and a second version identifier is made. A comparison of the first version identifier and the second version identifier is performed. A boot sequence from a recovery image is executed based on the comparison.

Abstract: A system may be provided that includes a random access memory, a non-volatile solid state memory, a serial non-volatile semiconductor memory, and a memory controller. The non-volatile solid state memory may include a boot block and a code partition. The serial non-volatile semiconductor memory stores a last written boot sector identifier. The memory controller may be configured to read the last written boot sector identifier from the serial non-volatile semiconductor memory and find a last written boot sector of the boot block based on the last written boot sector identifier read from the serial non-volatile semiconductor memory.

Abstract: An information handling system includes a processor, a controller hub, a shared higher bandwidth path coupling the processor to the controller hub, and an exclusive lower bandwidth path coupling the processor to the controller hub. The processor communicates system management information over the bandwidth path in response to a first set of criteria and communicates the information over the lower bandwidth path in response to the second set of criteria.

Abstract: A controller for a work machine includes a main board and a PC board. The main board includes a main controller that runs on a built-in work machine operating system, a first activator that activates the main controller when an activation signal for activating the controller is inputted, and an activation commander that outputs an activation-command signal to the PC board when the main controller becomes active. The PC board includes a PC controller that runs on an operating system for PCs, a network terminal, a network controller that outputs the activation signal to the main board when a specific signal for commanding activation is inputted, and a second activator that activates the PC controller when the activation-command signal outputted from the activation commander of the main board is inputted.

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

Abstract: The present disclosure relates system and method for automatic assignment of power domain and voltage domain to one or more SoC and/or NoC elements based on one or a combination of NoC and/or SoC specification/design, traffic specification, connectivity between SoC hosts that the NoC element in context is a part of, power specification (power domain and voltage domain of each host) of the hosts/SoC, and power profile(s) applicable for the NoC element in context. In another example implementation, power domain and voltage domain can be assigned to each SoC and/or NoC element based on pre-defined constraints and with an objective of reducing/minimizing static power consumption, reducing/minimizing hardware area, or identifying a tradeoff between the two parameters.

Abstract: Provided is distribution device that distributes time information to at least one sensor device, the distribution device including a storage unit that stores a time adjustment amount to be used for adjusting a local time, a calculation unit that calculates a time difference between a reference time and the local time, an adjustment unit that calculates an adjusted local time by adjusting the local time by an amount equal to or less than the time adjustment amount, when the time difference is greater than the time adjustment amount, and a distribution unit that distributes time information of the adjusted local time to the sensor device.

Abstract: The server includes a power supply apparatus; a power receipt terminal connected to a network and supplied with electric power fed to over the network; and a controller configured to perform state monitoring of the server by being supplied with electric power from the power supply apparatus, or electric power from the power supply apparatus and electric power from the power receipt terminal, and when supply of electric power from the power supply apparatus is quitted, the controller changes an electric power supply route so as to be supplied the electric power only from the power receipt terminal.

Abstract: Remotely awakening an electronic device, in which an apparatus includes a power supply to supply external power; a receiver for an electromagnetic signal; a capacitor connected to the receiver; a switching circuit connected to the capacitor; a controller, being part of the electronic device, connected to receive power from the switching circuit and to provide a keep awake signal to the switching circuit. The switching circuit to connect the controller with the capacitor when the capacitor is loaded with a predefined amount of power via the receiver, and responsive to the keep awake signal to disconnect the controller from the capacitor and to connect the controller with the power supply afterwards. The controller performs an initialization phase in response to receiving power and enables the keep awake signal after completing the initialization phase.

Abstract: A communication model in which application(s) above a hypervisor use a file system having one data access model (e.g., a block-based file system) to access an underlying storage device having another data access model (e.g., an object-based file system). This is accomplished via an intermediary component that converts input/output requests and responses from the file system data access model into the underlying storage device data access model, and vice versa. As an example, virtual machines operating a block-based file system using a hypervisor may interface through the intermediary component with an object-based storage device. Thus, the prolific use and availability of block-based file systems may be used compatibly with highly efficient object-based storage devices.

Abstract: A real-time-calibration circuit for multiple CPUs includes the CPUs for communication, for control and for acting as a panel board. The CPUs each have a real-time clock built therein. The CPU for communication is connected with an external real-time clock, and only the external real-time clock is connected with a battery. Through the CPU for communication, a standard time is obtained from an external network and provided to the external real-time clock for time calibration. Then a calibration value generated from the time calibration is fed back to the CPU for communication to be used by the real-time clock of the CPU for communication and the real-time clocks of the other CPUs, so as to prevent the CPUs from interfering communication during time calibration, and reduce the need of power and of batteries, thereby saving energy and costs and being friendly to the environment.

Abstract: An integrated circuit includes a multiple number of processor cores and a system management unit. The multiple number of processor cores each operate at one of a multiple number of performance states. The system management unit is coupled to the multiple number of processor cores, for setting performance states of the multiple number of processor cores. The system management unit boosts a first performance state of a first processor core of the multiple number of processor cores based on both a first temperature calculated from an estimated power consumption, and a second temperature based on a temperature measurement.

Abstract: A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register in the peripheral circuit is provided in an interface with a bus line. A power gate for controlling supply control is provided. The microcontroller can operate not only in a normal operation mode where all circuits are active, but also in a low power consumption mode where some of the circuits are active. A volatile memory and nonvolatile memory are provided in a register, such as a register of the CPU. Data in the volatile memory is backed up in the nonvolatile memory before the power supply is stopped. In the case where the operation mode returns to the normal mode, when power supply is started again, data in the nonvolatile memory is written back into the volatile memory.