Abstract: An apparatus and method for detecting defects on silicon dies on a silicon wafer (16) comprising an image acquisition system (10) and a computer (32) that determines a statistical die model by analyzing a random selection of dies (42) within a die matrix (37) and compares the statistical die model to matrices of silicon dies (38) to determine which silicon dies (38) have surface defects, is disclosed.

Abstract: A light emitting diode display package and method of fabricating a light emitting diode (LED) display package including a LED array display chip, fabricated of an array of LEDs, formed on a substrate, having connection pads positioned about the perimeter of the LED array display chip, a separate silicon driver chip having connection pads routed to an uppermost surface, positioned to cooperatively engage those of the display chip when properly registered and interconnected using wafer level processing technology. The display chip being flip chip mounted to the driver chip and having a layer of interchip bonding dielectric positioned between the space defined by the display chip and the driver chip. The LED display and driver chip package subsequently having selectively removed the substrate onto which the LED array was initially formed, thereby exposing the connection pads of the display chip and a remaining indium-gallium-aluminum-phosphide (InGaAlP) epilayer.

Abstract: Curved surfaces of a preform of thermoplastic adhesive provide improved regulation of heating and exclusion of gas as surfaces to be bonded are heated and pressed against the thermoplastic adhesive preform. Volume and thickness of the bond are controlled by the inclusion of a wire mesh embedded in a preform or through which the thermoplastic adhesive is pressed during bonding. The wire mesh also increases heat transfer through the adhesive in a regulated and even manner over the area of the bond or any desired portion thereof. Particulate or filamentary materials can be added to the thermoplastic adhesive for adjustment of coefficient of thermal expansion or further increase of heat transfer through the adhesive or both. The preform is preferably fabricated by molding, preferably in combination with die-cutting of a preform of desired volume from a web of approximately the same thickness as the completed bond.

Abstract: To provide a highly reliable semiconductor device which does not suffer from a crack in its package, a semiconductor chip 12 is mounted on a lead frame 11 with a bonding layer 13 between them, and they are sealed with a sealing resin 14. The lead frame 11 has a base member 11a essentially consisting of Cu and an oxide film 11b essentially consisting of an oxide of the base member 11a formed on the base member and having a thickness of about 50 nm or below. By controlling the oxide film 11b to a thickness of about 50 nm or below, an adhesion strength with the sealing resin 14 is improved greatly, so that a package crack does not occur even if a large thermal load is applied in a reflow process for mounting.

Abstract: A fabrication method for a chip size semiconductor package, includes providing a conductive package frame having a plurality of paddles which are each supported from the frame by a plurality of tie bars, adhering a semiconductor chip to each paddle, connecting each of the semiconductor chips to the frame by a plurality of wires, plating a conductive material onto each wire, forming an insulating layer on a surface of each semiconductor chip, cutting each wire to form a lead, and removing the plurality of tie bars to separate the completed package from the frame.

Abstract: An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus.

Abstract: Disclosed herein is a solder bump forming method and a sputter deposition apparatus used in this method which improves a bonding strength between a metal film having a solder bump forming region and an undercoating for the metal film. This method includes the steps of forming an opening through the undercoating, forming the metal film on the undercoating by a lift-off process so that the metal film is connected through the opening to an electrode pad formed on a substrate of a semiconductor device chip and has the solder bump forming region different from a region on the electrode pad, and forming a solder bump on the solder bump forming region of the metal film.

Abstract: A method for testing an integrated circuit situated on the top of a semiconductor substrate. The method includes the steps of focusing a photon onto a portion of the integrated circuit through an anti-reflective coating disposed on the back side of the semiconductor substrate and detecting the photon after the photon is reflected from the integrated circuit.

Abstract: A heat sink assembly includes a printed wiring board, a metal case and a circuit package containing a gallium arsenide field effect transistor heat dissipating circuit. The circuit package includes a metal slug formed integrally with the circuit package, the heat dissipating circuit being bonded to an obverse surface of the metal slug. The printed wiring board includes first and second metal lands, the first metal land being disposed on an obverse surface of the printed wiring board, the second metal land being disposed on a reverse surface of the printed wiring board. A solder film is formed bonded to and thermally coupling a reverse surface of the metal slug to the first metal land, and a plurality of solder posts are formed, each post bonding to and thermally coupling the first metal land to the second metal land. The metal case is pressed against the second metal land with a grease film of thermally conductive grease squeezed therebetween.

Abstract: A semiconductor-chip is bonded to a chip-carrier substrate by way of a gold-to-gold bonding interface. A vacuum chuck is provided to physically hold the semiconductor-chip in physical contact with, the chip-carrier substrate as static force, ultrasonic power, and an elevated temperature are applied to two mating gold surfaces that are formed by two continuous and physically mating gold layers. The bonded assembly is encased in a potting ceramic, or the bonded assembly is encased in a housing that includes a transparent cover that enables use as an optoelectronic semiconductor device.

Abstract: The present invention provides a method for forming a device on a wafer without peeling, in which the wafer has a substrate forming thereon a first dielectric layer forming thereon a first conducting layer having thereon a device area and an edge area. This method includes steps of a) forming a second dielectric layer on the device area and the edge area, b) forming a photoresist layer on the second dielectric layer, c) selectively removing the second dielectric layer, the photoresist layer, and the first conducting layer from and presenting thereby the device area and the edge area with a desired dielectric layer, and d) forming a metal film on the device area and the edge area.

Abstract: A multi-layer circuit structure including a plurality of substrate layers. At least one planar transmission line, including microstrip, stripline, or coplanar line, disposed on the plurality of substrate layers. A via transmission line connected to that at least one planar transmission line and extending through the plurality of substrate layers. The via transmission lines having the same topology as the at least one planar transmission line for providing wide frequency band transition between the via transmission lines and the at least one planar transmission line.

Abstract: A conductor (112) and method for attaching a surface mount device to the conductor (112), in which solder bumps (16) formed by the method are characterized as being accurately located on the conductor (112) and having a bump height and shape that provides stress relief during thermal cycles, minimizes bridging between adjacent bumps (16), allows penetration of cleaning solutions for removing undesirable residues, and enables the penetration of mechanical bonding and encapsulation materials between the chip and its substrate (10). Such benefits are achieved by forming the conductor (112) of a nonsolderable material, on which a solderable pillar (114) is formed. The pillar (114) is selectively formed to have a shape that determines the distribution and height of the solder bump (16) on the conductor (112).

Abstract: A molding machine for encapsulating electronic devices mounted on one side of a substrate, and having a ball-grid array, pin-grid array, or land-grid array on the opposite side, has a two member biased floating plate apparatus to compensate for variations in substrate thickness, and a gas collection/venting apparatus for relieving gases emitted from the non-encapsulated underside of the substrate.

Abstract: A semiconductor device has a flexible structure bonded to a semiconductor substructure to form a cavity. The flexible structure is bonded over a conducting feed-through without the feed-through interfering with a hermetic seal formed by bonding. One embodiment of the device includes depressions that contain edges of a diffused feed-through so that imperfections at the edge of the diffusion do not interfere with bonding. The flexible structure is bonded to elevated areas thus hiding the imperfections. In one embodiment, a first elevated region is surrounded by a second elevated region, and diffusion for the feed-through extends from an active region in the cavity across the first elevated region with edges of the diffusion being between the first and second elevated regions. The flexible structure can thus bond to the first and second elevated regions without interference from the edge of the diffused feed-through.

Abstract: An automated method for selectively locating fill pattern diffusion regions on a semiconductor substrate. In one embodiment, the present invention determines the locations of active diffusion regions on a semiconductor substrate. The present invention also determines the locations of interconnect lines on the semiconductor substrate. Next, the present invention creates a union of the location of the active diffusion regions on the semiconductor substrate and the location of the interconnect lines on the semiconductor substrate. The present invention uses this union to define allowable locations for placement of fill pattern diffusion regions on the semiconductor substrate such that the fill pattern diffusion regions are not disposed under the interconnect lines.

Abstract: Bonding pads are formed on a main surface of a semiconductor chip. An insulating layer having openings located on the bonding pads is formed on the main surface of the semiconductor chip. Base metal layers are formed on the bonding pads. A buffer coat film having a portion laid on a periphery of the base metal layer is formed on the insulating layer. Connection layers are formed on the base metal layers. First conductors are formed on the connection layers. A seal resin exposing only top surfaces of the first conductors is formed. Lumpish second conductors are formed on the top surfaces of the first conductor. Thereby, a resin seal semiconductor package can be made compact and it has improved electrical characteristics and high reliability.

Abstract: A method and apparatus are provided for handling planar structures, such as semiconductor wafers, with reduced breakage and cracking. The method includes the step of segmenting a wafer prior to grinding. The apparatus includes a segmented vacuum table for supporting wafer portions in position to be ground to a desired thickness. In another aspect of the invention, adhesive material is employed to individually secure wafer portions in position during the grinding process.

Abstract: The uppermost metal layer (metal-one) on a flip-chip packageable IC is modified to include at least one VCC pad, at least one ground pad, and at least one and preferably five test pads. Each pad is sized to be probe wafer-contactable, is and electrically coupled to appropriate vias formed in the IC. During IC fabrication but before the destination layer is fabricated, the IC is tested using a wafer probe that couples appropriate signals and power to the pads formed on the metal-one layer. If testing discloses a bug, it is possible to modify the IC metal-one traces, e.g., using FIB and then re-wafer probe test the IC. An insulating layer and destination layer may then be fabricated over what is known to be a good IC, and re-testing may occur. In this fashion, debugging diagnostics are made using testable ICs, and any metal-one revision may be tried and confirmed before changing the metal-one pattern for mass produced ICs.

Abstract: A method and system for fabricating electronic assemblies, such as multi chip modules, which include wire bonded semiconductor dice, are provided. Initially, dice having bond pads, and a substrate having corresponding bond pads, are provided. Using a wire bonding process, bonded connections are made between the bond pads on the dice, and the bond pads on the substrate. During the wire bonding process, electrical continuity in the bonded connections can be evaluated. Following wire bonding, but prior to subsequent processing of the assemblies, quick functionality tests can be performed to evaluate other electrical characteristics of the assemblies (e.g., gross functionality, open/short, pad leakage, cell defects). This permits defective assemblies to be identified prior to further processing. Once the assemblies have been completed, full functionality and parametric tests can be performed.