Abstract: An apparatus for detecting an open neutral condition in a split phase power system is described. The apparatus includes two powered lines providing output electricity to an electrical distribution system and a shared neutral line providing a grounded neutral to the first and second powered lines. The apparatus is configured for detecting when an open neutral condition is present in the split phase power system by determining when a power current is present on one or both of the first and second powered lines while a return current is not present on the neutral line; and in response to detecting that the open neutral condition is present, causing an interrupter to interrupt the power supplied by the first and second powered lines or to generate a signal indicating an open condition.

Abstract: Provided is a soft X-ray static electricity removal apparatus that has achieved an increase in the amount of ionized air discharged, with a simple structure. A soft X-ray static electricity removal apparatus (1) includes a soft X-ray generation device (90), a container (10), a soft X-ray shielding sheet (20), and an insulating layer (50). The soft X-ray generation device generates soft X-rays (92). The container (10) has an outlet (12) from which ionized air (100) that has been ionized with the soft X-rays flows out. The soft X-ray shielding sheet (20) is used at the outlet of the container and includes a first outer sheet (30), an interlayer sheet (34), and a second outer sheet (40) which are formed of a material opaque to the soft X-rays.

Abstract: A device includes an electrostatic discharge (ESD) protection switch and an ESD driver. The ESD driver is configured to receive a first voltage at a first terminal and receive a second voltage at a second terminal and includes a first trigger circuit and a first resistor. The first trigger circuit includes a first input terminal and a first output terminal. The first input terminal is configured to receive the first voltage. The first resistor is coupled between the first output terminal and the second terminal. When the first voltage received at the first terminal is a first overvoltage and a voltage difference between the first voltage and the second voltage is higher than a first voltage threshold, the ESD driver outputs a first trigger signal to turn on the ESD protection switch.

Abstract: A surge protection device with a high breaking capacity includes a housing with at least two lead-out electrodes, and a voltage limiting device and a thermal tripping mechanism that are installed in the housing. The voltage limiting device includes a voltage limiter, a first electrode and a second electrode that are positioned and installed in an insulating cover. The thermal tripping mechanism includes a fixed assembly, a movable assembly and a thermal trigger device. The fixed assembly and the movable assembly form a plurality of displacement switches arranged in series. The thermal trigger device is disposed in linkage with the movable assembly and includes a metal trigger sheet, a fusible alloy and an energy storage member. One end of the metal trigger sheet is fixed on the movable assembly, and the other end of the metal trigger sheet is fixed on the second electrode through welding by the fusible alloy.

Abstract: Described systems and methods allow the detection and quantitative estimation of changes in the properties of a liquid sample comprising living biological cells, the changes caused by exposure to a target analyte such as a toxin, drug, pesticide, etc. A variable stimulus such as an oscillating magnetic field is applied to the sample, inducing variations in a position or shape of a constituent of the sample. Such variations produce measurable variations in electric and/or optical properties of a sensor, variations which allow a precise quantification of changes due to exposure to the target analyte.

Abstract: An electrostatic discharge (ESD) protection circuit is configured to protect a target circuit that operates in a cryogenic temperature is provided. The ESD protection circuit connects a terminal of the target circuit and a ground potential with no connection to a bias potential. When the ESD protection circuit receives a voltage potential at the terminal of the target circuit, the ESD protection circuit (i) disallows electrical current to flow through from the received voltage potential when the device is at a cryogenic temperature and (ii) allows electrical current to flow through from the received voltage potential when the device is at a room temperature.

Abstract: In one embodiment, a protection circuit in a semiconductor device includes first and second transistors including gates electrically connected to a first node, and connected in series to each other between the first and second lines, third and fourth transistors including gates electrically connected to a second node between the first and second transistors, and connected in series to each other between the first and second lines, and a fifth transistor including a gate electrically connected to a third node between the third and fourth transistors, and provided between the second node and the second line. The protection circuit further includes an arithmetic circuit configured to perform calculation using a first signal received from the second node to output a second signal, and a sixth transistor configured to receive the second signal to output a control signal to the arithmetic circuit.

Abstract: A display substrate and a display apparatus are provided, the display substrate includes: a base substrate including a display area and a peripheral area surrounding the display area; a plurality of sub-pixel units in the display area; a plurality of data lines in the display area and electrically coupled to the plurality of sub-pixel units; a plurality of data transmission lines in the peripheral area on at least one side of the display area and electrically coupled to the plurality of data lines; a plurality of first pads and a plurality of second pads located between the plurality of first pads and the plurality of data transmission lines; a plurality of third pads between the plurality of first pads and the plurality of second pads; and a plurality of multiplexers between the plurality of second pads and the plurality of third pads.

Abstract: Disclosed is a reactance-injecting module and its method of use to balance the currents among the phases of polyphase electric power transmission lines or to manage power flow among alternate paths, where the reactance-injecting module has high-speed, dedicated communication links to enable the immediate removal or reduction of injected reactance from all phases of a phase balancing cluster when a fault is detected on any one of the multiple phases. The reactance-injecting module may communicate information on a detected fault to the other reactance-injecting modules of the phase balancing cluster within 10 microseconds after the fault is detected to allow the phase balancing cluster to eliminate injected reactance from all phases within a time that is short compared to a cycle of the alternating current, such as 1 millisecond after the fault is detected. This provides extremely fast neutralization of injected reactance to minimize interference with fault localization analyses.

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.

Abstract: An electronic device including a first transistor, a second transistor, a third transistor, and a resistance element is provided. The first transistor includes a first gate and is coupled between a first electrode and a second electrode. The second transistor includes a second gate, a third electrode, and a fourth electrode. The second gate is coupled to the second electrode. The third electrode is coupled to a control electrode. The third transistor includes a third gate, a fifth electrode, and a sixth electrode. The third gate is coupled to the control electrode. The fifth electrode is coupled to the fourth electrode. The sixth electrode is coupled to the second electrode. The resistance element is coupled between the third electrode and the first gate.

Abstract: A device includes a protected terminal, a reference terminal, and a rate-triggered circuit coupled to the protected terminal and to the reference terminal. The rate-triggered circuit is configured to provide an output voltage responsive to a ramp rate of a voltage at the protected terminal being greater than a rate threshold. The device also includes a transistor configured to shunt current from the protected terminal to the reference terminal responsive to the rate-triggered circuit output voltage, and a level-sensing circuit configured to turn off the transistor responsive to the voltage at the protected terminal being greater than a level-sense threshold.

Abstract: The present application relates to electrostatic protection circuit, integrated circuit and electrostatic discharge method.

Abstract: Embodiments relate to an electrostatic discharge (ESD) protection circuit and a chip. The ESD protection circuit includes: an ESD protection module, arranged inside a protected chip and connected to a protected circuit; and a control module, connected to the ESD protection module and configured to output a low-level signal to the ESD protection module to trigger the ESD protection module to discharge an electrostatic current when an ESD event occurs in the protected chip, and output a high-level signal to the ESD protection module to reduce a static leakage current of the ESD protection module when the ESD event does not occur in the protected chip.

Abstract: An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. an electronic device may include a first group III nitride transistor and an ESD protection circuit. The ESD protection circuit may include a first transistor, a second transistor, and a third transistor. The first transistor may have a source and a gate connected to each other and electrically connected to a gate of the first group III nitride transistor. The second transistor may have a source and a gate connected to each other and electrically connected to a source of the first group III nitride transistor. The third transistor may have a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a drain of the first transistor and to a drain of the second transistor, and a source electrically connected to the source of the first group III nitride transistor.

Abstract: An electrostatic discharge (ESD) protection circuit includes an ESD detector connected between a pad and a first power source and configured to generate a detection signal when ESD is detected at the pad, a switch transistor including a gate controlled by the detection signal and a source and a drain connected between the pad and the memory, and a leakage current prevention circuit including a first transistor including a first gate connected to a second power source and a source and a drain connected between the pad and a first node, and a second transistor including a second gate connected to the pad and a source and a drain connected between the first node and the second power source. The first node is connected to or in electrical communication with a bulk node of the switch transistor.

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.

Abstract: A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

Abstract: An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a diode and a second transistor. The diode has an anode electrically connected to a gate of the first group III nitride transistor. The second transistor has a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a cathode of the diode and a source electrically connected to a source of the first group III nitride transistor.

Abstract: An electrostatic protection circuit connected with an internal circuit is provided. The electrostatic protection circuit includes: a first circuit, a first diode connected in parallel with the first circuit, a second circuit, and a second diode connected in parallel with the second circuit. The first circuit is connected between a power supply pad and an internal circuit input terminal. The second circuit is connected between the internal circuit input terminal and a ground pad. The first circuit and the second circuit are diode-triggered silicon controlled rectifier circuits. The technical solution of the disclosure can improve electrostatic protection capability of a charged device model of a chip.