Abstract: Systems and methods for analyzing performance of a processing system are based on performance counters provided in trace points located at selected nodes of the processing system. A first transaction to be monitored is identified as a transaction to be monitored at a first trace point if the transaction is detected, by a performance counter, more than a threshold number of times at the first trace point. A first trace tag identifier is associated with the first transaction at the first trace point. The first transaction is identified at one or more other trace points based on the first trace tag identifier. Based on time stamps at which the first transaction is identified at the trace points, information such as trace information, latency, locality of a consuming device of the first transaction, etc. is obtained from the various trace points.

Abstract: Systems and methods are disclosed to perform early termination error recovery at a data storage device. A data storage device may be configured to perform error recovery operations in response to encountering an error while executing a host command, and terminate the error recovery operations prior to completion based on an error recovery time limit. Based on early termination of the error recovery operations, the storage device can add a storage location corresponding to the error to a scan list of storage locations on which to perform additional error recovery operations. In some embodiments, the host may set the error recovery time limit.

Abstract: Embodiments of the present invention provide a method, system and computer program product for trace capture of successfully completed transactions for trace debugging of failed transactions. In an embodiment of the invention, a method for trace capture of successfully completed transactions for trace debugging of failed transactions is provided. The method includes storing entries in a log with information pertaining to successfully completed transactions in a transaction processing system executing in memory of a host server, detecting a failed transaction in the transaction processing system, generating a trace for the failed transaction, and providing with the generated trace an entry from the log with information pertaining to a successful completion of the failed transaction.

Abstract: A method for predicting failure modes in a machine includes learning (31) a multivariate Gaussian distribution for each of a source machine and a target machine from data samples from one or more independent sensors of the source machine and the target machine, learning (32) a multivariate Gaussian conditional distribution for each of the source machine and the target machine from data samples from one or more dependent sensors of the source machine and the target machine using the multivariate Gaussian distribution for the independent sensors, transforming (33) data samples for the independent sensors from the source machine to the target machine using the multivariate Gaussian distributions for the source machine and the target machine, and transforming (34) data samples for the dependent sensors from the source machine to the target machine using the transformed independent sensor data samples and the conditional Gaussian distributions for the source machine and the target machine.

Abstract: A system for monitoring a virtual machine executed on a host. The system includes a processor that receives an indication that a failure caused a storage device to be inaccessible to the virtual machine, the inaccessible storage device impacting an ability of the virtual machine to provide service, and applies a remedy to restore access to the storage device based on a type of the failure.

Abstract: An application for testing is determined. A test script associated with the application for testing is determined. The application is tested using the test script. The testing requires transferring data form the application to an out-of-band channel.

Abstract: Methods and circuits are disclosed for error recovery in redundant processing systems. Respective instances of a software program are executed in lockstep on redundant processing circuits. Using a control circuit, in response to detecting a non-fatal error, an interrupt is generated and non-functioning ones of the processing circuits are disabled. The interrupt is serviced using the functional processing circuits operating in lockstep. In servicing the interrupt, a processing state of the processing circuits is stored and a reset of the processing circuits is triggered. Following the reset, the processing circuits are configured to operate in lockstep. The state of the processing circuits is restored to the stored processing state and a return from the interrupt is signaled. In response to the signaled return from interrupt, execution of the software program is resumed on the processing circuits in lockstep at a point at which the non-fatal error was detected.

Abstract: Disclosed herein are technologies directed to a feature ideator. The feature ideator can initiate a classifier that analyzes a training set of data in a classification process. The feature ideator can generate one or more suggested features relating to errors generated during the classification process. The feature ideator can generate an output to cause the errors to be rendered in a format that provides for an interaction with a user. A user can review the summary of the errors or the individual errors and select one or more features to increase the accuracy of the classifier.

Abstract: Techniques to provide direct access to backup data are disclosed. An indication is received to provide access to backup data backed up previously to a target device. The backup data as stored on the target device is used to spawn on the target device a logical volume corresponding to the backup data. Access to the logical volume as stored on the target device is provided to a production host.

Abstract: A method, system and computer program product are disclosed for recovery in a virtualized environment using remote direct memory access (RDMA). In one embodiment, the method comprises operating a virtual computer system on a physical computer system, and the virtual system maintains in a memory area a record of a state of the virtual system. In this method, when defined error conditions occur on the virtual system, RDMA is used to pull the record of the state of the virtual system from that memory area onto a standby computer. This record on the standby computer is used to re-initialize the virtual computer. Embodiments of the invention provide methods that provide a very fast recovery from a virtual machine fault or error, while requiring much fewer resources than standard approaches. In embodiments of the invention, one spare real computer system can be used for backing up several virtual systems.

Abstract: An electronic system includes: a host processor; a system memory, coupled to the host processor, includes data persistence regions identified by the host processor; a non-volatile storage device, including a fast path write (FPW) reserved area, configured to store user data from the system memory in a non-volatile media; and a power monitor unit, coupled to the host processor, configured to detect a power loss by a primary power failure detector and assert a power-loss detection control; and wherein the host processor is configured to engage a RAM flush driver for moving the content of the data persistence regions to a fast path write (FPW) reserved area in the non-volatile media when the power-loss detection control is asserted.

Abstract: Computer-implemented methods and apparatuses for application testing are provided. Such apparatuses may include a data repository that stores a copy of at least some of a set of stored reference data. Such apparatuses may also include a test data generation component that generates a set of input data for testing the application. The test data generation component may process a set of received input data and the set of stored reference data according to a data processing operation. The set of received input data and set of stored reference data may each comprise one or more attributes, each with at least one value. The test data generation component may generate the set of input data by selecting at least one value from the copy of the set of stored reference data, and outputting the selected at least one value in the generated set of input data for testing the application.

Abstract: The present invention provides for monitoring data file transmissions to determine patterns in data file transmissions and determining issues in a current data file transmission by comparing information associated with the patterns to attributes associated with the current data file transmission. In response to determining issues, dynamic alerts are generated and communicated to designated parties that notify the designated parties of the issues and prompt remedial actions. The present invention is able to monitor events that occur prior to data transmission (i.e., pipeline events) and, when such events are determined, through comparison of the patterns of attributes, to be abnormal or identify a fault, alerts may be generated and actions taken to eliminate or lessen the delay in the subsequent data transmission (i.e., adhere to predetermined data transmission timing requirements).

Abstract: A system and method of fuzz testing an on-line gaming system includes a host test bench system capable of generating a protocol template that can be used for identifying primitives in the data communications between a client device and the online gaming servers. The protocol template can then be used to identify primitives in initial communications between the client device and the online gaming servers and perform generation fuzz testing of those initial communications. The system also includes a game stream interceptor that can intercept streaming online gaming data in both directions between the client device and the online gaming system. The intercepted streaming online gaming data can be mutated to test the client device and the servers in the online gaming system.

Abstract: A workflow engine on a computing device is used to resolve a trouble ticket. Preliminary data is retrieved and one or more symptoms are received from a user device having a malfunction. The probability of each possible cause of the malfunction is determined. Upon determining that a probability of a mostly likely cause of the malfunction is above a predetermined threshold, a solution is provided. Upon determining that the probability of the most likely cause of the malfunction is not above the predetermined threshold, then entering a loop of performing diagnostic steps until the likely cause of the malfunction is above a predetermined threshold. Each diagnostic step is performed automatically, if the workflow engine determines that it can. If the diagnostic step cannot be performed automatically, the CSR is guided on how to accommodate the diagnostic step.

Abstract: A memory device may include: a plurality of memory cells; at least one address storage unit; a fail detection unit suitable for comparing first and second read data that are read from at least one memory cell selected among the plurality of memory cells to detect a fail, and storing an address of the selected memory cell in the address storage unit when the fail is detected; and a refresh control unit suitable for refreshing the memory cell corresponding to the address stored in the address storage unit at a higher frequency than the other memory cells.

Abstract: An input string, which includes exception data payload, is received at the API exception that resides in the upper management layer. The API exception is dedicated to receiving the exception data payloads. The API exception validates the input string. The API exception transmits the exception data payload to a lower management layer without the lower management layer knowing where the exception data payload was transmitted from.

Abstract: A method for providing backup power to power loads. The method includes a computer processor identifying an indication of a power failure to a computing system. The method further includes identifying a first active power load that is imposed on the computing system by one or more computing devices in the computing system. The method further includes responding to the power failure by activating a first IPU that is connected to the first active power load, identifying a power duration threshold for the first active power load, and determining whether a duration of power stored in the first IPU is less than the identified power duration. The method further includes responding to the determination that the duration of power stored in the first IPU is less than the identified power duration threshold of the first active power load by initiating a shutdown protocol for the first active power load.

Abstract: Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.

Abstract: A memory device includes a memory, a data interface, an error interface and a controller. The data interface communicates data to and from the memory device through an external main memory path. The error interface communicates error information from the memory device through an external system control path and that is separate from the main memory path. The controller is coupled to the data interface, the error interface, and the memory. The controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the memory and generates corrected data by encoding data written to the memory and decoding data read from the memory, generates error information, transmits the corrected data through the data interface, and transmits the error information through the error interface. The ECC controller records the error information in response to the ECC engine.