Patents Examined by Dinh: D.
  • Patent number: 5454116
    Abstract: A semiconductor integrated circuit has a clock input buffer, a set of clock drivers, an input buffer, an input latch, an output latch, and a three-state buffer. The clock input buffer produces a first intermediate clock signal in phase with an external clock signal and a second intermediate clock signal out of phase with the external clock signal. With the first intermediate clock signal applied, the set of clock drivers produce non-overlapping two internal clock signals, namely, a first internal clock signal in phase with the external clock signal and a second internal clock signal out of phase with the external clock signal. The input latch is controlled by either the first internal clock signal or the second internal clock signal and latches an output of the input buffer connected to an input/output terminal. The output latch is controlled by the second intermediate clock signal and the latch control signal and latches a signal to be outputted.
    Type: Grant
    Filed: February 18, 1993
    Date of Patent: September 26, 1995
    Assignee: NEC Corporation
    Inventors: Hisao Harigai, Hiroaki Suzuki