Abstract: A computer system is presented which includes an output driver circuit with a drive strength that varies depending upon the speed of a peripheral device being accessed, the frequency of a system clock signal, and/or the system configuration. Reducing drive strength when a slow peripheral device is being accessed, the frequency of the system clock signal is reduced, or bus loading is low reduces the occurrence of large switching transients and accompanying ground bounce, power supply droop, and radiated EMI. A power management unit produces a clock frequency control signal which controls the frequency of the system clock. In one embodiment, the output driver circuit includes an address storage unit, an address comparator unit, a bus loading storage unit, a control unit, and one or more adjustable drive circuits having an output terminal coupled to a signal line of a peripheral bus.

Abstract: A serial transmission control function for controlling serial transmission by means of only two transmission data and reception data signal lines is provided to the MPU 6 in the control section 4 of the semiconductor disk unit 1 so that the MPU 6 performs both general control and serial transmission control, whereby the size of the control substrate can be reduced and the control function can be improved.