Abstract: Decoding associated with a second error correction code and a first error correction code is performed. Ns first and second-corrected segments of data, first sets of parity information, and second sets of parity information are intersegment interleaved to obtain intersegment interleaved data, where the Ns segments of data, the Ns first sets of parity information, and the Ns second sets of parity information have had decoding associated with the first and the second error correction code performed on them (Ns is the number of segments interleaved together). Decoding associated with a third error correction code is performed on the intersegment interleaved data and interleaved parity information to obtain at least third-corrected interleaved data. The third-corrected interleaved data is de-interleaved.

Abstract: A method begins by a dispersed storage (DS) processing module selecting a set of distributed storage and task (DST) execution units for executing a task and determining dispersed storage error coding parameters for data. The method continues with the DS processing module dispersed storage error encoding the data in accordance with the parameters to produce a plurality of encoded data blocks and grouping the plurality of encoded data blocks into a plurality of encoded data block groupings. The method continues with the DS processing module partitioning the task into a set of partial tasks, outputting at least some of the plurality of encoded data block groupings to the set of DST execution units, and outputting the set of partial tasks to the set of DST execution units for execution of the set of partial tasks on the at least some of plurality of encoded data block groupings.

Abstract: Data objects can be delivered over a network using a file delivery system and universal object delivery and template-based file delivery. This might be done by forming source data into a sequence of data objects represented by symbols in packets, sending those to receivers on request, wherein a transmitter obtains a template file delivery table with delivery metadata for the data objects, and constructing a first transmission object identifier for a data object based on a transmission object identifier construction rule described in the template file delivery table. A receiver might receive packets, extract a second transmission object identifier, associate encoded symbols comprising the received data packet with the data object if the first transmission object identifier and the second transmission object identifier identify the same data object, and recover, at least approximately, the source data for the data object based on the encoded symbols associated with the data object.

Abstract: The present disclosure is directed to a system and method for encoding k input symbols, using a Reed-Solomon erasure correction code, into a longer stream of n output symbols for transmission over an erasure channel. The present disclosure is further directed to a system and method for recovering the original k input symbols from only (and any) k output symbols (out of the n output symbols) received over the erasure channel. A symbol is a generic data unit consisting of one or more bits that can be, for example, a packet. The systems and methods of the present disclosure provide for an adjustable code rate that can be readily adapted based on changing channel conditions without having to reconstruct the encoder/decoder. As a result, such an encoder/decoder can be referred to as rate-independent.

Abstract: A method for shortening latency of Chien's search and related circuit are disclosed. The method includes the steps of: determining a shifted factor, p; receiving a BCH codeword; computing a syndrome from the BCH codeword; finding an error-location polynomial based on the syndrome; and processing Chien's search for the error-location polynomial to find out roots thereof. p is a number of successive zeroes from the first bit of the BCH codeword, the Chien's search starts iterative calculations by substituting a variable of the error-location polynomial with a nonzero element in Galois Field, GF(2m), and the nonzero element ranges from ?p+1 to ?n, wherein n is a codelength of the BCH codeword and equals 2m?1, and m is a positive integer.

Abstract: Aspects of the invention relate to techniques for chain fault diagnosis based on dynamic circuit design partitioning. Fan-out cones for scan cells of one or more faulty scan chains of a circuit design are determined and combined to derive a forward-tracing cone. Fan-in cones for scan cells of the one or more faulty scan chains and for failing observation points of the circuit design are determined and combined to derive a backward-tracing cone. By determining intersection of the forward-tracing cone and the backward-tracing cone, a chain diagnosis sub-circuit for the test failure file is generated. Using the process, a plurality of chain diagnosis sub-circuits may be generated for a plurality of test failure files. Scan chain fault diagnosis may then be performed on the plurality of chain diagnosis sub-circuits with a plurality of computers.

Abstract: In one aspect, a computer system for managing occurrences of data anomalies in a data stream is provided. The computer system includes a processor in communication with the data stream. The processor is programmed to receive a first data stream from a phasor measurement unit. The processor is also programmed to calculate at least one singular value associated with the first data stream. The processor is further programmed to detect a first data anomaly within the first data stream using the at least one singular value. The first data anomaly occurs during a first time segment. The processor is also programmed to indicate the first time segment as containing the first data anomaly.

Abstract: The various implementations described herein include systems, methods and/or devices that may enhance performance of error control encoding. The method includes receiving information data and generating parity information based on an m×k parity matrix comprising an array of b×b circulant sub-matrices, including m columns of said sub-matrices, each column comprising k said sub-matrices. The method further includes dividing the information data into a plurality of b-sized trunks and generating m parity segments. Each parity segment consists of b bits, and each parity segment is generated by multiplying each of the k b×b circulant sub-matrices in a respective column of the parity matrix by a corresponding trunk of information data, where each multiplication of a b×b circulant sub-matrix by a corresponding trunk comprises b2 concurrent computations. The method further includes generating a codeword based on the information data and the m parity segments.

Abstract: A system and method for testing an integrated circuit using methodologies to reduce voltage drop during ATPG and LBIST testing. In one embodiment, delay elements may be added to a clock circuit used to generate the various clock signals that trigger the switching of the various electronic components. In another embodiment, logic circuitry may be added to a clock generation circuit to isolate clock domains in order to enable a clock signal in each clock domain in a specific pattern. In yet another embodiment, capture phases for LBIST testing may be made to be asynchrounous within each capture phase, such that data capture for one LBIST partition may be timed different from other capture phases for other LBIST partitions. Finally, a further embodiment ATPG circuitry may also be partitioned such that logic circuitry only enables one (or less than all) ATPG partition at a time.

Abstract: An apparatus having mapping and interface circuits. The mapping circuit (i) generates a coded item by mapping write unit bits using a modulation or recursion of past-seen bits, and (ii) calculates a particular state to program into a nonvolatile memory cell. The interface circuit programs the cell at the particular state. Two normal cell states are treated as at least four refined states. The particular state is one of the refined states. A mapping to the refined states mitigates programming write misplacement that shifts an analog voltage of the cell from the particular state to an erroneous state. The erroneous state corresponds to a readily observable illegal or atypical write sequence, and results in a modified soft decision from that calculated based on the normal states only. A voltage swing between the particular state and the erroneous state is less than between the normal states.

Abstract: Systems and methods are provided for using a product code having a first dimension and a second dimension to encode data, decode data, or both. An encoding method includes receiving a portion of user data to be written in the first dimension, and computing first parity symbols with respect to the first dimension for the portion of user data. Partial parity symbols with respect to the second dimension are computed for the portion of user data and are used to obtain second parity symbols for the portion of user data. A decoding method includes decoding a first codeword in the first dimension. When the decoding the first codeword in the first dimension is successful, a target syndrome of a second codeword in the second dimension is computed based on a result of the decoding of the first codeword, wherein the first codeword partially overlaps with the second codeword.

Abstract: A computer-implemented method, computer program product, and computing system is provided for managing quality of service for communication sessions. In an implementation, a method may include determining network condition associated with a communication session. The method may also include calculating one or more anticipated performance attributes for each of a plurality of error correction codes based on the network condition. The method may also include determining a quality of experience metric for each of the plurality of error correction codes based on the calculated one or more anticipate performance attributes for each of the plurality of error correction codes. The method may further include establishing one of the plurality of error correction codes for the communication session based on the quality of experience metric for each of the plurality of error correction codes.

Abstract: A method begins by a processing module encoding data based on a decode threshold parameter and a pillar width parameter to produce a set of encoded data slices and selecting a local area network (LAN) pillar width value of encoded data slices of the set of encoded data slices for storage in LAN available memories, wherein the LAN pillar width value is based on the decode threshold parameter, the pillar width parameter, and quantities of the LAN available memories. The method continues with the processing module selecting a wide area network (WAN) pillar width value of encoded data slices of the set of encode data slices for storage in a dispersed storage network (DSN) memory of a wide area network, wherein the WAN pillar width value is based on the decode threshold parameter and the pillar width parameter.

Abstract: A computer-implemented method, computer program product, and computing system is provided for managing quality of service for communication sessions. In an implementation, a method may include determining network condition associated with a communication session. The method may also include calculating one or more anticipated performance attributes for each of a plurality of error correction codes based on the network condition. The method may also include determining a quality of experience metric for each of the plurality of error correction codes based on the calculated one or more anticipate performance attributes for each of the plurality of error correction codes. The method may further include establishing one of the plurality of error correction codes for the communication session based on the quality of experience metric for each of the plurality of error correction codes.

Abstract: A stopping criterion for a turbo-encoding method. The criterion is based on a state metrics calculated by a forward-backward recursion in a coding trellis of an elementary encoder. If, for at least one elementary decoding stage, forward state metrics of a last symbol of a block or backward state metrics of a first symbol of a block exceeds a first threshold, the turbo-decoding iterations are stopped. If it is not the case, it is further checked whether the state metrics exceeds a second threshold and if the absolute value of the difference between the current state metrics and the state metrics obtained at the previous iteration lies below a given margin. In the affirmative, the turbo-decoding iterations are stopped and a hard decision is taken on extrinsic values.

Abstract: A circuitry is proposed for the correction of errors in a possibly erroneous binary word v?=v?1, . . . , v?n relative to a codeword v=v1, . . . , vn, in particular 3-bit errors containing an adjacent 2-bit error (burst error). The circuitry comprises a syndrome generator and a decoder. A modified BCH is used wherein n? column vectors of a first BCH code submatrix are paired as column vector pairs so that a componentwise XOR combination of the two column vectors of each column vector pair produces an identical column vector K that is different from all column vectors of the first BCH submatrix. A second BCH submatrix comprises corresponding column vectors as the third power, according to Galois field arithmetic, of the column vector in the first BCH submatrix. The syndrome generated by the syndrome generator can be checked against the columns of the first and second submatrices.

Abstract: A method of reading from a memory module which includes a plurality of memories is provided. The method includes reading data corresponding to a plurality of burst length units from the plurality of memories; correcting an error of the read data using a storage error correction code; and outputting the error corrected data by a unit of data corresponding to one burst length unit.

Abstract: A method for matrix expansion is disclosed. In this method, a Progressive Edge Growth (“PEG”) expanding of an H matrix by a coder is used to provide an expanded H matrix. An Approximate Cycle Extrinsic Message Degree (“ACE”) expanding of the expanded H matrix by the coder is used to provide a parity check matrix for a code. The ACE expanding includes initializing a first index to increment in a first range associated with a PEG expansion factor, expanding each non-zero element in the expanded H matrix with a random shifted identity matrix for the first range, initializing a second index to increment in a second range associated with the first index and an ACE expansion factor, and performing an ACE detection for each variable node in the second range for the variable nodes of the parity check matrix. The coder outputs information using the parity check matrix.

Abstract: Disclosed are various embodiments for in-band management of Ethernet links utilizing a bit-interleaved parity (BIP) block in a transmission frame. According to various embodiments, a bit-interleaved parity error code may be generated for a monitored portion of network data for transmission in a first bit-interleaved parity block. Subsequently, network management data may be encoded in a plurality of bits for transmission in a second bit-interleaved parity block according to a predefined block code, wherein the predefined block code generates the plurality of bits to maintain a DC balance between the bit-interleaved parity error code and the plurality of bits.

Abstract: A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.