Abstract: A method includes: introducing a gas including gallium, an ammonia gas, and a gas including a p-type impurity to a reactor and forming a first p-type nitride semiconductor layer on a first light-emitting layer in a state in which the reactor has been heated to a first temperature; lowering a temperature of the reactor from the first temperature to a second temperature; introducing an ammonia gas with a first flow rate to the reactor and increasing the temperature of the reactor from the second temperature to a third temperature; and introducing a gas including gallium, an ammonia gas with a second flow rate, and a gas including an n-type impurity to the reactor, and forming a second n-type nitride semiconductor layer on the first p-type nitride semiconductor layer in a state in which the reactor has been heated to the third temperature.

Abstract: Examples of an integrated circuit with a contacting gate structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a memory cell that includes a plurality of fins and a gate extending over a first fin of the plurality of fins and a second fin of the plurality of fins. The gate includes a gate electrode that physically contacts the first fin and a gate dielectric disposed between the gate electrode and the second fin. In some such examples, the first fin includes a source/drain region and a doped region that physically contacts the gate electrode.

Abstract: An optoelectronic component and a method for manufacturing an optoelectronic component are disclosed. In an embodiment an optoelectronic component includes a diffractive optical element comprising at least one conversion material and a light source configured to emit primary radiation, wherein the conversion material is encapsulated in the diffractive optical element, and wherein the conversion material is arranged in a beam path of the primary radiation and is configured to convert the primary radiation at least partially into secondary radiation.

Abstract: A bi-directional optical module includes a substrate, at least one first light-emitting diode (LED), and at least one second LED. The first LED is disposed on a surface of the substrate. The first LED has a first reflection surface and a first light-outlet surface that are opposite to each other, and the first light-outlet surface is away from the substrate relative to the first reflection surface. The second LED is disposed on the same surface of the substrate. The second LED has a second reflection surface and a second light-outlet surface that are opposite to each other, and the second light-outlet surface is close to the substrate relative to the second reflection surface. The substrate has at least one light-transparent area that is not occupied by the first LED and the second LED.

Abstract: An electronic chip, system, and method includes a power block including a power source configured to provide power to components of the electronic chip and a relay circuit coupled to the power source and a ground plane. The electronic chip further includes chip package having a first major side and a second major side, the power block secured to the second major side, the chip package comprising electrical connections, disposed on the second major side, to be secured with respect to a circuit board, and interconnect circuitry, electrically coupling the power block to ground, comprising a plurality of conductive layers, a conductive through hole, electrically connecting a first pair of the plurality of conductive layers, having a first width, and a via, electrically connecting a second pair of the plurality of conductive layers, having a second width less than the first width.

Abstract: A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip.

Abstract: An embodiment provides a semiconductor device comprising: a semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and a plurality of recesses extending through the second conductive semiconductor layer and the active layer and arranged up to a partial region of the first conductive semiconductor layer; a plurality of first electrodes arranged inside the plurality of recesses and electrically connected to the first conductive semiconductor layer; a second electrode electrically connected to the second conductive semiconductor layer; a first conductive layer electrically connected to the plurality of first electrodes; a second conductive layer electrically connected to the second electrode; and an electrode pad electrically connected to the second conductive layer, wherein the electrode pad comprises a first electrode pad and a seco

Abstract: Provided are a light-emitting device and a display apparatus. The light-emitting device includes: sub-pixels located on an array substrate, the sub-pixels each includes a first electrode and a second electrode that are disposed opposite to each other, and a quantum migrating layer between the first electrode and the second electrode. The quantum migrating layer includes a non-light-exiting region and a light-exiting region corresponding to a backlight source. Transparent charged particles and quantum dots, which can be driven by an electric field to migrate in the light-exiting region and the non-light-exiting region, are encapsulated in an accommodating cavity of the quantum migrating layer. When there are quantum dots gathered in the light-exiting region, the quantum dots are excited to emit light; when there is no quantum dot in the light-exiting region, the light emitted by the backlight source directly passes and exits through the light-exiting region.

Abstract: A method for manufacturing a MEMS device includes disposing at least one bonding portion having a smaller bonding area in a region where an airtight chamber will be formed, and disposing a metal getter on a bonding surface of the bonding portion. According to this structure, when substrates are bonded to define the airtight chamber, the metal getter is squeezed out of the bonding position due to the larger bonding pressure of the bonding portion with a smaller bonding area. Then, the metal getter is activated to absorb the moisture in the airtight chamber. According to the above process, no additional procedure is needed to remove the moisture in the airtight chamber. A MEMS device manufactured by the above manufacturing method is also disclosed.

Abstract: A structure and a formation method of hybrid semiconductor devices are provided. The structure includes a substrate and a fin structure over the substrate. The fin structure has a channel height. The structure also includes a stack of nanostructures over the substrate. The channel height is greater than a lateral distance between the fin structure and the stack of the nanostructures. The structure further includes a gate stack over the nanostructures. The nanostructures are separated from each other by portions of the gate stack.

Abstract: A method of manufacturing a semiconductor structure includes the following operations. A wafer includes a crystal orientation represented by a family of Miller indices comprising <lmn>, wherein l2+m2+n2=1. A first chip and a second chip are over the wafer. A first edge of the first chip and a second edge of the second chip are adjacent to each other. A boundary extending in a direction between the first edge and the second edge is formed. A first included angle between the first direction and the crystal orientation is greater than or equal to 0 degree and less than 45 degrees.

Abstract: A light emitting device including a substrate, a first semiconductor layer disposed on the substrate, a mesa including a second semiconductor layer and an active layer disposed on the first semiconductor layer, a first contact electrode contacting the first semiconductor layer, a second contact electrode contacting the second semiconductor layer, a passivation layer covering the first contact electrode, the mesa, and the second contact electrode, and including a first opening disposed on the first contact electrode and a second opening disposed on the second contact electrode, and first and second bump electrodes electrically connected to the first and second contact electrodes through the first and second openings, respectively, in which the first and second bump electrodes are disposed on the mesa, the passivation layer is disposed between the first bump electrode and the second contact electrode, and the first contact electrode includes an alloy layer.

Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

Abstract: A semiconductor device, including a substrate, and a deposit layer and a semiconductor layer formed sequentially on the substrate. The semiconductor layer has selectively disposed therein a first region, a second region and a contact region. A gate electrode is disposed on the first region and the semiconductor layer via a gate insulating film. A source electrode is formed in contact with the contact region and the second region. A drain electrode is disposed on the back surface of the substrate. The source electrode has a first titanium (Ti) film, and a titanium nitride (TiN) film, a second Ti film, and a metal film containing aluminum (Al) sequentially formed on the first Ti film. The source electrode may further include another TiN film, on which the first Ti film is formed.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A light emitting apparatus is provided. The light emitting apparatus includes a frame structure having a bottom side and a reflective lateral side connecting to the bottom side; and a first light emitting element and a second light emitting element on the bottom side of the frame structure. The first light emitting element is configured to emit a first light having a first wavelength range along a first direction. The second light emitting element is configured to emit a second light having a second wavelength range along a second direction. The first direction and the second direction are substantially opposite to each other. The reflective lateral side of the frame structure is configured to reflect the first light having the first wavelength range into a first reflected light and reflect the second light having the second wavelength range into a second reflected light.

Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device structure also includes a first fin structure over the semiconductor substrate and surrounded by the isolation structure and a stack of nanostructures over the first fin structure. The nanostructures are separated from each other. The semiconductor device structure further includes a second fin structure over the semiconductor substrate. The second fin structure has an embedded portion surrounded by the isolation structure and a protruding portion over the isolation structure. The embedded portion is separated from the protruding portion by a distance.

Abstract: A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.

Abstract: In a light emitting device, a columnar part includes a first semiconductor layer, a second semiconductor layer different in conductivity type from the first semiconductor layer, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer is disposed between the substrate and the light emitting layer, the light emitting layer includes a first layer, and a second layer larger in bandgap than the first layer, the first semiconductor layer has a facet plane, the first layer has a facet plane, the facet plane of the first semiconductor layer is provided with the first layer, and ?2>?1, in which ?1 is a tilt angle of the facet plane of the first semiconductor layer with respect to a surface of the substrate provided with the laminated structure, and ?2 is a tilt angle of the facet plane of the first layer provided to the facet plane of the first semiconductor layer with respect to the surface of the substrate.