Abstract: A field-programmable gate array (FPGA) with reconfigurable threshold logic gates for improved performance, power, and area (PPA) is provided. This disclosure describes a new architecture for an FPGA, referred to as threshold logic FPGA (TLFPGA), that integrates a conventional lookup table (LUT) with a complementary metal-oxide-semiconductor (CMOS) digital implementation of a binary perceptron, referred to as a threshold logic cell (TLC). The TLFPGA design described herein, combined with a new logic mapping algorithm that exploits the presence of both conventional LUTs and TLCs within the basic logic element (BLE) block, achieves significant improvements in all the metrics of PPA. The TLCs of embodiments described herein are capable of implementing a complex threshold function, which if implemented using conventional gates would require several levels of logic gates. The TLCs only require seven static random-access memory (SRAM) cells and are significantly faster than the conventional LUTs.

Abstract: In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.

Abstract: A microwave antenna apparatus comprises a package module comprising a semiconductor unit, an antenna unit arranged on a first side of the package module and a redistribution layer group arranged on a second side of the package module opposite the first side, and an electromagnetic band gap structure, EBG, module coupled to the redistribution layer group of the package module.

Abstract: A single flux quantum (SFQ) cell may include SFQ circuitry to implement a logic function that generates logic values of a set of outputs based on logic values of a set of inputs. The SFQ circuitry may instantaneously update logic values of the set of outputs in response to changes in logic values of the set of inputs. The SFQ circuitry may include at least one SFQ non-destructive set-reset flip-flop.

Abstract: A circuit can include a first Josephson junction (JJ), a second JJ, and a third JJ coupled in parallel using superconducting inductors. The first JJ, the second JJ, and the third JJ can be biased using one or more JJ-based current sources.

Abstract: Techniques are described for a lighting system in which light sources are controllable using signals sent over a wireless mesh network. During a commissioning process, a user interface (UI) may present a representation of nodes (e.g., light sources, sensors, controllers, etc.) that are broadcasting a wireless advertising signal. In response to a selection of a particular node, a wireless message may be sent to instruct the selected node to provide a visual indication of its presence, such as a flashing light. The visual indication may enable a user to discern the physical location of the node, such that each node may be added to the mesh network and, in some instances, to a group of nodes. The UI may also enable the definition of scenes, where each scene describes the brightness level or other operating characteristics of particular light source(s) and/or group(s) of light sources when the scene is active.

Abstract: A semiconductor device which includes a termination circuit coupled to a first pad and suitable for providing a termination resistance according to a first control code and a second control code during a normal operation in which data are input and output through the first pad; a stress replica circuit suitable for replicating a stress applied to the termination circuit during the normal operation and for generating a detection code during a second calibration mode; a first calibration circuit suitable for adjusting the first control code to match an impedance of a resistor part coupled to a second pad to an external resistor during a first calibration mode; and a second calibration circuit suitable for generating the second control code by adjusting the first control code according to the detection code during the second calibration mode.

Abstract: An on-die termination circuit may include a resistance combination circuit, a first calibration circuit, a second calibration circuit, and a termination circuit. The resistance combination circuit may have an additional resistance value for setting a combined resistance value by combining the additional resistance value with a reference resistance value, and may be configured to set the additional resistance value based on a second calibration code. The first calibration circuit may be configured to generate a first calibration code corresponding to the reference resistance value or the combined resistance value according to a calibration sequence. The second calibration circuit may be configured to generate the second calibration code corresponding to the first calibration code. The termination circuit may be coupled to an input/output pad, and may be configured to set a termination resistance value corresponding to the first and second calibration codes.

Abstract: Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.

Abstract: A closet lighting system incorporates a light strip that extends around an inside perimeter of a closet doorway and is configured to automatically turn on when motion is detected in the doorway. Motion may be a closet door opening or a person moving into a closet doorway, either walking into or reaching in. A closet lighting system has one or more activity sensors to detect the motion in the closet doorway. A first activity sensor may be configured proximal to the control system or the connected end of the light strip to the controller. A second activity sensor may be configured on a distal end of the light strip and may send a motion signal through the light strip, such as through a data line or through a power line. A motion signal may a voltage signal passed through the power line below a voltage to activate the lights.

Abstract: An LED lighting device is disclosed. The example LED lighting device includes at least one LED circuit having at least two LEDs, where an LED of the at least two LEDs is configured to emit light of a different color temperature or wavelength than at least one other LED of the at least two LEDs. The example LED lighting device also includes a switch connected to the at least one LED circuit and configured to dim at least one of the LEDs of the at least two LEDs that are configured to emit light of the different color temperature or wavelength to enable user selection of different color temperatures or wavelengths of light to be emitted by the at least one LED circuit. The at least one LED circuit and the switch are integrated into the LED lighting device.

Abstract: An impedance calibration circuit includes first and second calibration circuits, a switch circuit and a control circuit. The first calibration circuit is coupled to an external resistance, and generates a first voltage. The second calibration circuit generates second and third voltages. The switch circuit is coupled to the first and second calibration circuits. The switch circuit selectively provides the first, second, and third voltages to first and second nodes. The control circuit is coupled to the first and second nodes. The control circuit generates first, second, and third control signals according to voltages of the first and second nodes. In a first time interval, the switch circuit provides the first voltage to the first and second nodes. In a second time interval, the switch circuit provides the second voltage to the first and second nodes, or provides the second and third voltages respectively to the first and second nodes.

Abstract: An antenna device and an electronic device including the same are provided. The antenna device includes a housing that includes a first plate, a second plate facing a direction opposite to the first plate, and a side member surrounding a space between the first plate and the second plate, a display viewable through at least a portion of the first plate, an antenna assembly disposed within the housing wherein the antenna assembly includes a first printed circuit board, a second printed circuit board, at least one structure interconnecting the first printed circuit board and the second printed circuit board and including conductive paths, a plurality of conductive patterns, and a wireless communication circuit, a flexible printed circuit board, and a third printed circuit board.

Abstract: A method of routing interconnects of a field programmable gate array including: a plurality of logic tiles, and a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects to interconnect logic tile networks of the logic tiles, the method comprises: routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles. After routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles. The start/end point of each tile-to-tile interconnect in the first plurality and the second plurality of tiles is independent of the start/end point of the other tile-to-tile interconnects in the first and second plurality, respectively.

Abstract: Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e.g., by the memory device). For example, a channel used for data communications with a second device (e.g., a controller) may initially be in a state of active termination. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting calibration signals on the channel and detecting an offset associated with a reference voltage. The memory device may use the detected offset and the reference voltage to identify signals transmitted to the memory device over the channel.

Abstract: The impedance of a loopstick antenna is directly modulated utilizing a mechanically actuated magnetoelastic material preferably placed in the core (or center) of looped wires forming the loopstick antenna. Using one or more mechanical actuators the permeability in the center of the loopstick antenna can be modulated at a rapid rate (such as with data or audio information), allowing the magnetic field outside of the antenna to be modulated at large bandwidths without requiring switches or modulators capable of high voltage thus reducing the overall complexity and cost of the transmitter. The external magnetic field is created by an AC source which is preferably impedance matched to the loopstick antenna by means of a matching network and is FM modulated according to a modulating signal applied to the one or more mechanical actuators.

Abstract: A load control device may be configured to control an electrical load, such as a lighting load. The load control device may include a first terminal adapted to be coupled to an alternating-current (AC) power source, and a second terminal adapted to be coupled to the electrical load. The load control device may include a bidirectional semiconductor switch, a filter circuit, and a control circuit. The bidirectional semiconductor switch may be coupled in series between the first terminal and the second terminal, and be configured to provide a phase-control voltage to the electrical load. The filter circuit may be coupled between the first terminal and the second terminal. The control circuit may be configured to render the bidirectional semiconductor switch conductive and non-conductive to control an amount of power delivered to the electrical load, and be configured to adjust the impedance and/or filtering characteristics of the filter circuit.

Abstract: An antenna device includes an antenna, a first ground conductor, and an artificial magnetic conductor. The artificial magnetic conductor is sandwiched between the antenna and the first ground conductor, and separated from the antenna and the first ground conductor. The first ground conductor includes a first cutaway part on one end side, the first cutaway part having a substantially rectangular shape.

Abstract: A memory device includes a pad region having a flag pad separated from an external host, and a signal pad connected to the external host. A bank region is provided having a plurality of memory cells therein. An on-die-termination (ODT) setting circuit is provided, which is configured to receive a control command including first data corresponding to termination resistance requested by the host, and a ODT enable signal. The setting circuit is configured to generate second data corresponding to the ODT resistance. An ODT enable circuit is provided, which is configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal. A resistor circuit is provided, which is configured to connect the ODT resistance to the signal pad using the second data.

Abstract: A phase compensation lens antenna comprises: an antenna array comprising a plurality of antennas; and a planar lens disposed parallel to the antenna array, wherein the planar lens has unit cells disposed in a straight line pattern or an open curve pattern, and the unit cells can correct the phase of a radio wave radiated from the antenna array, based on the permittivity.