Abstract: The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA.

Abstract: A dynamic termination logic driver, the driver capable of launching signals at a driving end of a transmission line and terminating signals at a receiver end of the transmission line, controls slew rate over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance. The driver includes a pull up circuit having an impedance, the pull up circuit including a pull up output circuit and a buffer circuit, the pull up output circuit including a parallel pull up circuit, a pull up output control circuit, and a pull up slew rate control circuit, wherein the parallel pull up circuit and the pull up output control circuit are coupled in parallel.

Abstract: A semiconductor integrated logic circuit device with a sequential circuit includes a transferring section, an inverting section, a bistable circuit section, and a blocking section. The transferring section is provided between first and second nodes, and transfers a data signal from the first node to the second node in response to a clock signal. The inverting section is provided between the second node and a third node, and inverts the data signal on the second node to output on the third node as an inverted data signal. The bistable circuit section is connected to the second and third nodes, and holds the data signal. The blocking section is provided between the bistable circuit and the first node, and blocks off sub-threshold leakage current.

Abstract: In electronic systems, signaling problems frequently occur when a device is driving a signal on a line to an incorrect level at a particular point in time. When production schedules do not permit fixing the defects in the errant device, programmable logic has been employed to work around the problems caused by the defective device. Higher device speeds and increasingly complex bus protocols have made the technique of singly using programmable logic, more difficult to implement. The addition of bidirectional switches integrated with and controlled by programmable logic in a monolithic integrated circuit allows the programmable logic device to respond more quickly while at the same time consuming less printed circuit board space. Additionally, the invention provides for termination of the isolated device and/or signal line stubs.

Abstract: Buffers having an output pull-up transistor controlled by the input signal, an output pull-down transistor and a pull-down transistor control circuit. A current source provides a current that is divided between the pull-up transistor and the pull-down transistor control circuit to maintain the desired output voltage. A boost capacitor is coupled between the output and the pull-down transistor control circuit to provide good dynamic response to the circuit even in the presence of substantial capacitive loads on the output. In addition a second capacitor is coupled between the pull-down transistor control circuit and a fixed voltage to provide a low frequency pole internal to the circuit. The connection of the boost capacitor to the pull-down transistor control circuit and the connection of the second capacitor to the pull-down transistor control circuit are separated by a substantial resistance, allowing the effect of each capacitor to be substantially independent of each other.

Abstract: A constant slew rate amplifier has a precision internal slew rate control reference, that generates respective positive-going and negative-going voltages, associated with corresponding excursions in the input signal. These slew rate-defining voltages are decoupled from the line, making it possible to drive the line with an amplified output signal that faithfully follows the input signal and conforms with prescribed slew rate and rise/fall time specifications, irrespective of the capacitance of the line. In addition, the constant slew rate amplifier of the present invention is configured to minimize power dissipation during non-transitional signal conditions, while providing substantial current to rapidly drive the line from one state to another in accordance with the input signal.