Abstract: A totally D.C. balanced and bit-rate independent digital clock encoding technique is applicable to a variety of digital signalling systems, including fiber optic digital signalling. Each of successive event cells of the clock signal is demarcated by clock transitions of opposite polarity, so that each clock cycle contains two event cells, one of which is redundant. For a first binary data value, such as a `0`, a pair of unmodified successive event cells of the clock signal are provided as an output. Namely, the clock signal is unaffected, so that both halves of a complete, unmodified clock cycle are reproduced `as is` as the encoded clock output. For a second binary data value, such as a `1`, an event cell is modified by inserting a pulse, of finite duration, less than the duration of the event cell, the pulse being delayed with respect to a leading clock transition of the pair of alternating, opposite clock transitions of the event cell.

Abstract: A transceiver module for coupling between cells in a distributed intelligence network and a twisted pair line. The module receives power from the line and provides power to its respective cell. At the end of transmitting a packet, the transceiver transmits a code violation, then an anti-code violation to dissipate energy in the line. This is followed by clamping the line for the dead time between packets. N transceivers may be connected (without a cell) to form a repeater. The transceiver module may be used in a network having free topology; that is, an ideal transmission line, with terminators is not needed.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.

Abstract: The method for executing coding subprocesses and decoding subprocesses calculates a first time interval from a current point to a variable output point of the coded output signals. Similarly, a second time interval from the current point to an output point of the decoded output signals is calculated. Second, a total processing time of a subsequent coding and decoding subprocesses is calculated. The subsequent subprocesses are both allowed to be subsequently executed. Finally, one subprocess to be subsequently executed is selected from the subsequent coding and decoding subprocesses by comparing the total processing time with a smaller one of the first and the second time intervals.

Abstract: A digital phase-locked loop having a jitter limited to one-half of a period of the reference clock comprises a generator circuit and a control circuit. The input clock is defined by a plurality of rising edges and falling edges. The generator circuit receives a reference clock and generates the output clock. The phase of the output clock is one of a plurality of selectable phases such that the difference in phases between the output clock and the input clock is limited to one-half of a period of the reference clock once the DPLL locks to the input clock. The control circuit receives the input clock, the reference clock, and the output clock and provides a selection input to the generator circuit to make the phase of the output clock selectable upon each rising edge and upon each falling edge of the input clock.

Abstract: A method and apparatus for attenuating jitter in digital signals. A recovered clock is derived from the digital signal and the digital signal is stored in a buffer. The derived clock is input to an input counter which counts a predetermined number of degrees out of phase with an output counter. When the input counter is at a maximum counter value, the output counter value is latched to the address inputs of a ROM look-up table, which outputs a coefficient to a numerically controlled oscillator (NCO). The NCO includes a low frequency portion that adds the coefficient successively to itself and outputs a carry out (CO) signal. A high frequency portion of the NCO receives a high frequency clock and preferably divides down the high frequency clock to a clock frequency which is centered at the desired output frequency. The high frequency portion preferably includes an edge detect circuit that receives the CO signal and adjusts the frequency of the output clock to produce a compensation clock.

Abstract: Bus coupler operates with a transformer and a comparator which is connected downstream in the signal-processing branch. The comparator threshold is raised as a function of the signal in the case of larger signals relative to small signals.

Abstract: A method for RF communication between transceivers in a radio frequency identification system that improves range, decreases multipath errors and reduces the effect of outside RF source interference by employing spread spectrum techniques. By pulse amplitude modulating a spread spectrum carrier before transmission, the receiver can be designed for simple AM detection, suppressing the spread spectrum carrier and recovering the original data pulse code waveform. The data pulse code waveform has been further encrypted by a direct sequence pseudo-random pulse code. This additional conditioning prevents the original carrier frequency components from appearing in the broadcast power spectra and provides the basis for the clock and transmit carrier of the transceiver aboard an RFID tag. Other advantages include high resolution ranging, hiding transmissions from eavesdroppers, and selective addressing.

Abstract: A system and technique for detecting a recurring signal, for example, a synchronization pulse contained in an information signal stream modulated on a carrier signal, wherein the recurring signal has a known duration (.tau.) and a known period (T). The signal carrier is demodulated such that the recurring signal exhibits a certain characteristic amplitude variation over its duration .tau., and the demodulated signal carrier is sampled at intervals less than .tau. thereby obtaining signal samples exhibiting the amplitude variation of the recurring signal. The signal samples are applied to an input of a coincidence network including at least one delay circuit which provides a delay corresponding to the period T of the recurring signal to a passing signal sample, and input and output terminals of each delay circuit are coupled to different inputs of an associated coincidence gate circuit. Each coincidence gate circuit produces an output whenever its input signal samples coincide with one another.

Abstract: A converter which is connected to a modulation/demodulation equipment having a first interface and to a terminal equipment having a second interface is disclosed. The converter includes a first connector for electrically connecting the converter to the modulation/demodulation equipment; a second connector for electrically connecting the converter to the terminal equipment; a signal converting circuit connected to the first connector and the second connector, for converting a signal input from the first connector into a signal which follows the second interface, the converted signal being output to the second connector, and for converting a signal input from the second connector into a signal which follows the first interface, the converted signal being output to the first connector; and a power supply circuit for supplying power to the modulation/demodulation equipment via the first connector.

Abstract: A physically compact, multichannel wireless communication transceiver architecture employs overlap and add or polyphase signal processing functionality, for wideband signal processing, together with a sample rate. A receiver section receives a plurality of multiple frequency communication channels and outputs digital signals representative of the contents of the plurality of multiple frequency communication channels. The receiver section contains an FFT-based channelizer that processes the digital signals output by a wideband digital receiver and couples respective channel outputs to a first plurality of digital signal processor units, which process (e.g. demodulate) respective ones of the digital channel signals and supply processed ones of the digital channel signals at respective output ports for distribution to an attendant voice/data network.

Abstract: A method for transmitting pieces of synchronized picture data having the same data length of which each include a synchronizing signal, an identifying code, pieces of compressed picture data having different data lengths and an error correcting code in that order is disclosed. To correctly decode each of the compressed picture data, it is required to start a decoding operation from a head address of each of the compressed picture signal. Therefore, in cases where a head address of a piece of compressed picture data exists in a piece of synchronized picture data, an existence information flag for informing the existence of the head address, an address pointer for indicating an address of the head address, and a block number for indicating a position of the compressed picture data having the head address are added just after the identifying code to correctly decode the compressed picture data and other pieces of following compressed picture data in the synchronized picture data.

Abstract: A physically compact, multichannel wireless communication transceiver architecture employs overlap and add or polyphase signal processing functionality, previously applied to narrowband speech analysis research, for wideband signal processing. A receiver section receives a plurality of multiple frequency communication channels and outputs digital signals representative of the contents of the plurality of multiple frequency communication channels. The receiver section contains an FFT-based channelizer that processes the digital signals output by a wideband digital receiver and couples respective channel outputs to a first plurality of digital signal processor units, which process (e.g. demodulate) respective ones of the digital channel signals and supply processed ones of the digital channel signals at respective output ports for distribution to an attendant voice/data network.

Abstract: A signal transmission system (10) is provided that comprises a transmitter circuit (12) which transmits a signal through a transmission line (16) to a receiver circuit (14) using the current mode of signal transmission. A steady state current is supplied by a steady state current source (22). An active state current is provided by an active current source (20). A boost circuit (18) is provided to reduce delay associated with the transmission line (16) by increasing charge to the transmission line and providing additional discharge path from the transmission line during transitions of the signal propagating along transmission line (16).

Abstract: A system for receiving a complex modulation digital signal using a temporal equaliser including an estimator supplying correction parameters. This system includes: at least one peripheral control loop, the estimator of which uses at least one of said correction parameters, the peripheral control loop having an operating range separate from that of the temporal equalizer; and a temporal discriminator detecting inactive areas of the estimator of each peripheral control loop to enable operation of the temporal equalizer in such a way as to prevent interaction between the temporal equalizer and the peripheral control loop. The peripheral control loop can be a Mueller and Muller-type pointing estimator and/or a Leclert and Vandamme-type carrier recovery device.

Abstract: A threshold detector for digital signal transmission systems using a transmission channel, in particular for transmission to mobiles, calculates a set of coefficients f.sub.n belonging to the group comprising a set of coefficients c.sub.n of the correlation between a first series of digital samples x.sub.n received by the receiver and a second series of reference digital samples p.sub.n known to the receiver, in order to acquire synchronization of the system, and a set of coefficients h.sub.n of an estimate of the impulse response of the transmission channel, when the system is already synchronized. It also calculates a decision variable A such that: ##EQU1## where L and N are predetermined integers. The device has many applications in mobile radio systems, for example for acquisition of synchronization in DS-CDMA systems or for optimizing the transmission channel estimate.

Abstract: An equalizer for use in a receiving system of a code transmission system has a plurality of series-connected delay elements, a plurality of coefficient units for weighting tap output signals extracted in parallel from the delay elements, an adder for adding output signals from the coefficient units, and a tap coefficient setting circuit for adjusting the weighting of the coefficient units. The tap coefficient setting circuit has a multiplier for multiplying a differential signal, the differential signal representing a difference between an output signal from the equalizer and a predetermined reference signal, and the tap output signals, a variation detecting circuit for being supplied with an output signal from the multiplier and detecting a variation of tap coefficients, and an accumulating circuit for outputting established tap coefficients based on an output signal from the variation detecting circuit.

Abstract: A Radio Frequency (RF)-band tuner stage is combined with a quadrature downconverter stage in a single shielded enclosure as an RF-to-baseband pulse amplitude modulated tuner suitable for receiving RF-band signals from an LNB or the like and converting the signals directly to signals in a desired digital format. The bandwidths within the two stages are optimized for digital PAM demodulation, such as PSK or QAM, and certain functions are shared, such as automatic gain control and carrier tracking information. Electronically switchable attenuators and voltage-variable gain controlled amplifiers, in connection with a low-phase-noise local oscillator employing a microstrip resonator, provide for over 70 dB of dynamic range. The IF frequency and bandwidth are selected so that voltage-variable tunable bandpass filters of conventional design may be used to obtain over 40 dB of radio frequency image rejection necessary for reception of PAM signals.

Abstract: A frequency synthesizer includes a voltage-controlled oscillator, frequency dividing circuits, a signal source, phase comparing circuits, an adding circuit, a converting circuit and a control circuit. The frequency dividing circuits divide an output supplied thereto from the voltage-controlled oscillator with frequency-dividing ratios of 1/N and 1/(N+1) where N is an arbitrary integer. The signal source outputs a reference frequency signal. The phase comparing circuits phase-compare a signal divided by N supplied thereto from one frequency dividing circuit and a signal divided by (N+1) supplied thereto from another frequency dividing circuit and the reference frequency signal from the signal source.

Abstract: A synchronous pseudo-noise (PN) code sequence generating circuit generates a plurality of PN code sequences which should be synchronized with each other. A feedback-type PN code generator generates a master PN code sequence. Each of N code converters, which are provided for each of N channels, converts the master PN code sequence to a PN code sequence of the corresponding channel in accordance with a mask pattern unique to the corresponding channel. The mask patterns for each channel are stored in the corresponding mask memory.