Patents Examined by Donald L. Morin
  • Patent number: 5510651
    Abstract: The present invention includes a semiconductor device having a layer including an elemental metal and its conductive metal oxide, wherein the layer is capable being oxidized or reduced preferentially to an adjacent region of the device. The present invention also includes processes for forming the devices. Substrate regions, silicon-containing layers, dielectric layers, electrodes, barrier layers, contact and via plugs, interconnects, and ferroelectric capacitors may be protected by and/or formed with the layer. Examples of elemental metals and their conductive metal oxides that may be used with the present invention are: ruthenium and ruthenium dioxide, rhenium and rhenium dioxide, iridium and iridium dioxide, osmium and osmium tetraoxide, or the like.
    Type: Grant
    Filed: November 18, 1994
    Date of Patent: April 23, 1996
    Assignee: Motorola, Inc.
    Inventors: Papu D. Maniar, Reza Moazzami, C. Joseph Mogab
  • Patent number: 5412228
    Abstract: A semiconductor switching device having gate-controlled regenerative and non-regenerative conduction modes includes a P-N-P-N thyristor and a diverter region in a semiconductor substrate. Regenerative conduction can be initiated by electrically connecting the thyristor's cathode region and first base region in response to a first bias signal. Non-regenerative conduction can also be initiated by electrically connecting the thyristor's second base region to the diverter region in response to a second bias signal, after regenerative conduction has been initiated. Alternative, non-regenerative conduction can be initiated by electrically connecting the thyristor's second base region to the diverter region and then electrically connecting the thyristor's first base region to the cathode region.
    Type: Grant
    Filed: February 10, 1994
    Date of Patent: May 2, 1995
    Assignee: North Carolina State University
    Inventor: Bantval J. Baliga
  • Patent number: 5034797
    Abstract: A semiconductor device having a CMIS structure for forming a static random access memory is disclosed which device can increase the packing density of the memory and reduce the stand-by power thereof. In this semiconductor device, a first MISFET of a first conductivity type is formed on and a substrate, a second MISFET of a second conductivity type is formed over the first MISFET with a first insulating film therebetween to form a stacked CMIS structure. The second MISFET is made up of a first conductive film, a second insulating film and a second conductive film, with the source, drain and channel regions of the second MISFET being formed in the first conductive film. A first resistive drain region is formed between the channel and drain regions of the first conductive film so that an impurity of the second conductivity type is contained in the first resistive drain region at a lower concentration than in the drain region, or the first resistive drain region is substantially undoped.
    Type: Grant
    Filed: March 22, 1990
    Date of Patent: July 23, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Yamanaka, Yoshio Sakai, Takashi Hashimoto, Takashi Nishida, Satoshi Meguro, Shuji Ikeda, Eiji Takeda
  • Patent number: 4985751
    Abstract: A resin-encapsulated semiconductor device is of the structure wherein a silicon chip on a die pad is encapsulated with a molding resin. The rear surface of the die pad remote from the silicon chip, preferably the entire surfaces of the elements are treated with a primer, typically a silane coupling agent and a low stress epoxy resin encapsulant is used, preventing the encapsulating resin from separating and cracking upon subsequent dipping in solder bath.
    Type: Grant
    Filed: September 8, 1989
    Date of Patent: January 15, 1991
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Toshio Shiobara, Takashi Tsuchiya, Hisashi Shimizu