Abstract: Apparatus and methods for communicating a communications controller with a connected device over a serial bus is provided. The connected device is connected to the bus at one of a plurality of addresses, and the method includes sending a first request to the device over the bus at a first address; waiting for an acknowledgement of the first request by the device; and establishing communication with the connected device if the acknowledgement of the first request is received.

Abstract: In one general aspect, methods and devices for use with multiple communications protocols automatically determine which communications protocol to use when connected to a system bus. Signals transmitted on the system bus are monitored to determine what communications protocol the system bus is using. After determining which communications protocol the system is using, a compatible communications protocol is selected from one of several communications protocols stored in a device's memory. As a result, a user may connect a device to the system bus without having to determine which communications protocol is used by the system bus. Furthermore, suppliers may stock a single type of device that is compatible with multiple communications protocols reducing overhead associated with stocking devices. In addition, a device may be switched between systems without regard to the communications protocol of the device or system.

Abstract: A system and method avoids passive release of interrupts in a computer system. The computer system includes a plurality of processors, a plurality of input/output (I/O) devices each capable of issuing interrupts, and an I/O bridge interfacing between the I/O devices and the processors. Interrupts, such as level sensitive interrupts (LSIs), asserted by an I/O device coupled to a specific port of the I/O bridge are sent to a processor for servicing by an interrupt controller, which also sets an interrupt pending flag. Upon dispatching the respective interrupt service routine, the processor generates two ordered messages. The first ordered message is sent to the I/O device that triggered the interrupt, informing it that the interrupt has been serviced. The second ordered message directs the interrupt controller to clear the respective interrupt pending flag. Both messages are sent, in order, to the particular I/O bridge port to which the subject I/O device is coupled.

Abstract: Transmitting data across a scalable, flexible speed, serial bus in a communication protocol independent manner.

Abstract: System and method for supporting split transactions on a bus. The method may comprise processing a periodic frame list of external bus data frame by frame, and traversing each frame node by node. When a save place node is encountered in a first frame, the traversing jumps to a destination node pointed to by the save place node in a second frame, and continues the traversing there. When a restore place node is encountered when traversing the nodes in the second frame, the traversing returns to the node after the save place node in the first frame and continues the processing in the first frame. The method may be implemented on a system that comprises a processor, a memory, an internal bus, and an external bus controller. The external bus controller and the external bus data may support one or more versions of the Universal Serial Bus standard.

Abstract: A data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one implementation, a data processing system includes at least first through third processing units, data storage coupled to the plurality of processing units, and an interconnect fabric. The interconnect fabric includes at least a first data bus coupling the first processing unit to the second processing unit and a second data bus coupling the third processing unit to the second processing unit so that the first and third processing units can transmit data traffic to the second processing unit. The data processing system further includes a control channel coupling the first and third processing units.

Abstract: An interface system capable of providing pre-emptive arbitration among multiple agents comprises an interface including at least a first agent and a second agent which share the interface for transferring data, the second agent having priority over the first agent for access to the interface. A pre-emptive arbiter provides arbitration between the first agent and the second agent when at least one of a first transfer request signal is asserted by the first agent for requesting access to the interface by the first agent and a second transfer request signal is asserted by the second agent for requesting access to the interface by the second agent. The pre-emptive arbiter is capable of synthesizing a transfer completion signal on the interface for preempting access of the first agent to the interface so that access may be granted to the second agent.

Abstract: A bus reset control module associated with a fibre-SCSI bridge manages target resets sent from a fibre bus to one or more SCSI buses to reduce or eliminate unnecessary bus resets of SCSI buses having sequential devices, such as tape storage drives. The bus reset control module accepts target resets from a fibre bus host to intercept the initiation of bus resets and communicates with target devices of the SCSI bus to determine whether the target devices are faulty. The bus reset control module issues bus resets to SCSI buses having a faulty target device but prevents issuance of bus resets to SCSI buses that do not have a faulty target device so that a sequential device interfaced with a SCSI bus is not subject to a bus reset if all devices associated with the SCSI bus are operating properly.

Abstract: A method and apparatus is provided for managing a controller embedded in a south bridge. The method includes determining if the south bridge of a processor-based system is configured to operate in a slave mode or a master mode, and polling one or more sensors in the processor-based system for status values in response to determining that the south bridge is configured to operate in the master mode. The method further includes receiving requests from a network interface card to access sensors internal to the south bridge based on determining that the south bridge is configured to operate in the slave mode.

Abstract: A method for communicating data is provided that includes storing one or more physical connectors associated with an input/output card and configuring the input/output card to a selected one of a slave, master, and passive mode. An identification for the input/output card may be provided to an end user, the identification reflecting a selected configuration parameter associated with the input/output card.

Abstract: An apparatus for providing packets in a peripheral interface circuit of an I/O node of a computer system. The apparatus includes a buffer that may be configured to accumulate data received on a first bus. The apparatus further includes a control unit coupled to the buffer which may be configured to transmit a data packet containing a first number of bytes of the data in response to detecting that any of the bytes of the data is invalid. The control unit may be further configured to transmit the data packet containing a second number of bytes of the data in response to detecting that all of the bytes are valid.

Abstract: Coded requests are received from Memory Port Interfaces (608 and 612) and stored into Outgoing Queue (604). Coded requests are also received from Transaction Pipeline (610), some of which may be linked requests. In response to each linked request stored in Outgoing Queue (604), multiple bus requests are generated by Outgoing Queue (604) and assembled by Assembler (602) and placed onto Bus Interface (620).

Abstract: A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface. An interrupt handler adjusts dynamic Packet and/or Latency values to control how many packets the interface may accumulate, or how much time the interface may wait after receiving a first packet, before it can signal a corresponding interrupt to a host processor and forward the accumulated packet(s). The interrupt handler maintains a Trend parameter reflecting a comparison between recent sets of packets received from the interface and the Packet parameter. The Packet value is decreased or increased as packet traffic ebbs or flows. When the Packet value is incremented from a minimum value, a Fallback mechanism may be activated to ensure a relatively rapid return to the minimum value if an insufficient amount of traffic is received to warrant a non-minimum Packet value. The Latency value may be increased as the processor's workload increases.

Abstract: A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.

Abstract: A circuit arrangement permits a microcontroller wirebond pad to be configured to be an analog or digital input or output. The circuit arrangement uses any of a plurality of switching configurations to selectively determine the use of the wirebond pad under control of the microcontroller's processor. The microcontroller can be configured using configurable analog and configurable digital blocks to perform any of a plurality of functions with certain of the pinouts determined under program control.

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

Abstract: A select circuit including a first device bridge to communicate a first stream of information between a first Serial ATA bus and a storage device bus. A second device bridge to communicate a second stream of information between a second Serial ATA bus and the storage device bus. A controller, in response to a select signal, to enable one of the first bridge device and the second bridge device to control a flow of the first stream of information and the second stream of information between the storage device bus and the first and second Serial ATA buses.

Abstract: A system on a chip has functional blocks accommodated by at least one system bus, and an external bus for accommodating communication with external blocks. A single multi-jurisdictional bus arbiter has programmable rankings for assigning priorities to requests from blocks that are masters for either one of the both buses. Software and methods are also provided for assigning the priorities. The requests are analyzed with respect to which of the buses they require, and then priorities are assigned to maximize bus utilization, with increased speed for a system on a chip. In addition, a multi-jurisdictional multi-channel direct memory access block can be a master block for the system bus or the external bus.

Abstract: A method and system for a pipelined bus interface macro for use in interconnecting devices within a computer system. The system and method utilizes a pipeline depth signal that indicates a number N of discrete transfer requests that may be sent by a sending device and received by a receiving device prior to acknowledgment of a transfer request by the receiving device. The pipeline depth signal may be dynamically modified, enabling a receiving device to decrement or increment the pipeline depth while one or more unacknowledged requests have been made. The dynamic modifications may occur responsive to many factors, such as an instantaneous reduction in system power consumption, a bus interface performance indicator, a receiving device performance indicator or a system performance indicator.

Abstract: If a block read cannot be used to read out from a configuration ROM information, the number of times of issue of a quadlet read request increases. This degrades the processing efficiently of a device that issues the request. In addition, the bus occupation ratio of a 1394 serial bus by the request becomes high, and the speed of processing through the 1394 serial bus decreases. To solve these problems, information stored in the configuration ROM area of a device is read out, and it is determined on the basis of the readout information that configuration information identical to the configuration ROM information is stored in an address area (block readable area) different from the configuration ROM area, the offset is changed, and the configuration information is read out from the address area different from the configuration ROM area.