Patents Examined by Douglas L. Owens
  • Patent number: 6677670
    Abstract: A flexible circuit substrate 11 has mounting regions 111, 112 and 113 on which electronic components 121, 122 and 123 are mounted, respectively. The flexible circuit substrate 11 is structured in such a manner that the mounting regions 111-113 are folded on top of the other over the base region 110 in a predetermined order (f1-f3). An integrated spacer 13 is superposed and affixed to the flexible circuit substrate and supports the electronic components 121-123 when the mounting regions 111-113 are folded on top of the other. The integrated spacer 13 has thick regions 131 and thin regions 132.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: January 13, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Yoichiro Kondo
  • Patent number: 6472710
    Abstract: A field MOS transistor having a high withstand voltage is disclosed. An island region of an epitaxial layer is surrounded by a heavily-doped isolation layer and a lightly-doped isolation layer formed thereon. A channel region is formed in the island region so as to assume the same doping level as that of the lightly-doped isolation layer. A region is formed below the island region so as to assume the same doping level as that of the heavily-doped isolation layer, thus supplying a back gate voltage to the transistor. The channel formation region is formed simultaneously with formation of the lightly-doped isolation layer, and the region below the island region is formed simultaneously with the heavily-doped isolation layer. As a result, manufacturing processes can be simplified.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: October 29, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tomohide Terashima
  • Patent number: 6426249
    Abstract: A metal capacitor formed as part of metal dual damascene process in the BEOL, of a wafer. A lower plate (27) of the capacitor is sandwiched between an insulating layer (25) and a dielectric layer (29). The insulating layer on an opposite side abuts a layer of metalization (23, 24) and the dielectric layer separates the lower plate of the capacitor from an upper plate (59) of the capacitor. A portion (27A) of the lower plate projects into a via (37) adjacent to it that is filled with copper (63). The via projects up to a common surface with the upper plate but is electrically isolated form the upper plate. The via also extends down to the layer of metalization.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: July 30, 2002
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Geffken, Anthony K. Stamper