Abstract: Embodiments of the present invention recite a method of preserving data on a hard disk drive. In one embodiment, a copy of data is read from at least one sector of a hard disk drive and stored in a memory location of the hard disk drive. At least a portion of the data in the memory location of the hard disk drive is then replaced to create a modified copy of data. A copy of the modified copy of data is then stored in a non-volatile memory location of the hard disk drive. Finally, the data from the at least one sector is replaced with the modified copy of data.

Abstract: A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation costs. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction.

Abstract: In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed.

Abstract: A method for operating a computer storage system is disclosed. One or more data storage devices are configured to store a data content of a data container. A data structure having a plurality of permitted modification times (mtimes) is generated, the mtimes to control modifying a data stored in the data container. An I/O operation is performed by the storage system in response to a selected mtime. A request for the I/O operation is received from a client, and the data structure having a plurality of permitted modification times (mtimes) is generated in response to the request. The selected mtime is transmitted to the client, and an I/O operation is requested by the client in response to the selected mtime. The I/O operation is performed as an atomic I/O operation.

Abstract: A method is disclosed that includes converting a first command to a second command. The first command is configured to control a first type of storage unit, while the second command is configured to control a second type of storage unit. The first type of storage unit is a secondary storage unit. The second type of storage unit is a primary storage unit.

Abstract: The invention provides a system and method for reducing pin count in an integrated circuit (IC) when interfacing to a synchronous dynamic random access memory (SDRAM). The SDRAM has a plurality of address lines and a plurality of data lines. The method includes connecting together the plurality of data lines and the plurality of address lines. The IC interfaces to the SDRAM through the connected plurality of address lines and the plurality of data lines.

Abstract: In one embodiment, the present invention includes a method for protecting a value to be stored in a register of a register file with a first level of protection if the value is predicted to be used for a first time period, and protecting the value with a second level of protection if the value is predicted to be used for a second time period. Other embodiments are described and claimed.

Abstract: A computer system for preventing data loss that includes: a first storage system having a data storage extent for storing data sent from a host computer; a second storage system having at least one actual replicated data storage extent associated with the data storage extent; an archive appliance having a storage medium associated with the replicated data storage extent in the second storage system; and a data copy unit for controlling copy processing for reading data from the data storage extent in the first storage system and writing the read data to a first actual replicated data storage extent in the second storage system in accordance with specific configuration information. The system also has a connection switching unit for changing the specific configuration information so that a second actual replicated data storage extent, instead of the first actual replicated data storage extent, is associated with the data storage extent.

Abstract: A data processing apparatus is provided comprising processing logic for issuing access requests when access to data is required, with each access request specifying a memory address associated with the data the subject of the access request. Access control logic is used to perform an access control operation to check for each access request whether the specified memory address is accessible by the processing logic. Further, a table is provided having a plurality of entries, each entry identifying an address range and an associated action. On occurrence of one or more predetermined events, the access control logic references the table to determine whether the specified address is within the address range identified by an entry of the table. If so, the associated action specified in that entry is invoked, whereas otherwise the access control logic causes any action indicated by the access control operation to be performed.

Abstract: A method and system for dynamic memory allocation and sharing in electronic systems. Embodiments include multi-channel signal processing, including continuously receiving multiple channels, wherein each channel comprises a discrete signal, and processing the multiple channels in a signal processing component on a time-multiplexed basis. Processing the multiple channels includes configuring the signal processing component for one of a plurality of operational modes, including allocating a memory into areas for storage of types of data, wherein certain areas are accessed by certain signal processing subsystems in certain manners. Configuring includes configuring the signal processing component to operate in different modes concurrently for different channels.

Abstract: A communication network, networking device and method is provided herein for locating (i.e., searching for) an interval of numbers i within a set of numbers N given a point P. The search algorithm provided herein provides fast search speed (e.g., requires only one memory access) with minimum storage requirements (e.g., consumes up to, but not exceeding, N entries within a memory device).

Abstract: Managing a cache memory includes providing at least one spillover slot, stored in the cache memory, that contains information about a plurality of cache data slots transferred from the cache memory to a local disk. The spillover slot has a metadata portion with information about cache data slots transferred from the cache memory to the local disk and has a catalog portion with entries that point to different sections of the metadata portion. Each section of the metadata portion corresponding to information about one of the cache data slots transferred from the cache memory to the local disk.

Abstract: Systems and methods can provide mirrored virtual targets and online synchronization and verification of the targets while avoiding deadlock, inconsistencies between members of the target, and false verification failures. A lock within the storage switch can limit the number of outstanding commands for a physical target to one during synchronization and verification operations. In one embodiment, a lock can be implemented as one or more resource tables maintaining an indication of the number of transfer ready signals available from physical targets. During typical write operations, deadlock can be avoided by determining whether each physical target for the mirrored operation can issue a transfer ready signal prior to issuing a command to the physical target. When a synchronization or verification operation begins, the maximum available number of transfer ready signals for each target can be decremented to one in order to limit the total number of outstanding commands for each target to one.

Abstract: Easily implemented randomization within a flash memory EEPROM reduces the NAND string resistance effect, program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. The randomization may be code generated pseudo randomization or user driven randomization in different embodiments. User driven commands, the timing of which cannot be predicted may be used to trigger and achieve a high level of randomization. Randomly altering the encoding scheme of the data prevents repeated and long term storage of specific data patterns. Even if a user wishes to store the same information for long periods, or to repeatedly store it, it will be randomly encoded with different encoding schemes, and the data pattern will therefore be varied.

Abstract: A technique to implement an integrated multidimensional sorter is to store data such that it may be retrieved in a sorted fashion. Entries are stored into a memory according to time stamp value, and the time stamp value is divided into multiple portions. The memory is organized as a pointer memory. An integrated multidimensional sorter may be implemented using integrated circuit technology using one or more integrated circuits. These integrated circuits may be used in management of network traffic, and provides quality of service (QoS) control.

Abstract: A method for managing host system power consumption is provided. The host system includes host memory and external memory. The method initiates with providing a processor in communication with a memory chip over a bus. The memory chip is external memory. Then, a usage measurement of the external memory is determined. If the usage measurement is below a threshold value, the method includes copying data from the memory chip to the host memory and terminating power to the memory chip. In one embodiment, the power is terminated to at least one bank of memory in the memory chip. In another embodiment, an amount of reduction of the external memory can be determined rather than a usage measurement. In yet another embodiment, an address map is reconfigured in order to maintain a contiguous configuration. A graphical user interface and a memory chip are provided also.

Abstract: A machine-accessible medium may contain program instructions that, when executed by a processor, may cause the processor to perform at least one operation including searching a virtual hash page table (VHPT) using a region identifier and a virtual page number of a virtual address, and a default page size corresponding to the region identifier to locate a virtual address translation in the VHPT. The operation performed may further include searching the VHPT using the region identifier, the virtual page number, and at least one utilized page size to locate a virtual address translation in the VHPT if a virtual address translation is not located during the search of the VHPT using the region identifier, virtual page number, and default page size. The operation performed may also include inserting the located virtual address translation into a translation cache once a virtual address translation is located.

Abstract: The disclosed embodiments support the backup of the contents of a media library, or a portion thereof, on one or more storage mediums. More particularly, the contents of the media library may include one or more media items and/or playlists. Once backed up, the contents stored on the storage mediums may be restored to the media library.

Abstract: A CAM device having two execution pipelines includes control logic and a CAM core. The CAM core includes a plurality of independently searchable CAM arrays for storing CAM words. The control logic receives a first request that selects any number of the CAM arrays for a first compare operation, and receives a second request that selects any number of the CAM arrays for a second, separate compare operation. The control logic determines whether the same CAM array is selected by both requests. If not, the control logic schedules the first and second compare operations to be executed simultaneously in the CAM core. Otherwise, the control logic schedules the first and second compare operations for sequential executionuses a suitable arbitration technique to determine the order in which the first and second compare operations will be executed in the CAM core.

Abstract: A data processing apparatus for writing data to a recording medium having a predetermined file system configured therein includes the following elements: an insertion portion that removably holds the recording medium, the data processing apparatus writing data to the recording medium inserted in the insertion portion; an insertion/removal detector that detects that the recording medium is inserted in or removed from the insertion portion; a writing state storage unit that stores, when the insertion/removal detector detects removal of the recording medium, a data writing state upon removal of the recording medium; and a restoration/analysis determining unit that determines, when the insertion/removal detector detects insertion of the recording medium, whether it is necessary to perform analysis regarding restoration of the file system configured in the inserted recording medium on the basis of the state stored in the writing state storage unit.