Abstract: Provided are a semiconductor element bonding apparatus and a semiconductor element bonding method that do not cause a bonding material to protrude and also ensure adhesion, even when there are variations in a thickness of a semiconductor element or a workpiece and even when there are projections and depressions on surfaces. A semiconductor element bonding apparatus includes disposing means for disposing a workpiece and a semiconductor element at positions facing each other, moving means for moving the workpiece or the semiconductor element in a vertical direction, displacement measuring means for measuring displacement of the workpiece or the semiconductor element in the vertical direction, load measuring means for measuring a contact load between the workpiece and the semiconductor element with the bonding material interposed therebetween, and elastic modulus calculating means for calculating an elastic modulus from results of the measurement by the displacement measuring means and the load measuring means.

Abstract: A method for manufacturing an organic solar cell according to an exemplary embodiment of the present application comprises: preparing a substrate; forming a first electrode on the substrate; forming a photoactive layer on the first electrode; drying the photoactive layer with a wind force of 0.01 Mpa to 0.07 Mpa; and forming a second electrode on the photoactive layer.

Abstract: A semiconductor memory cell comprising an electrically floating body. A method of operating the memory cell is provided.

Abstract: A semiconductor manufacturing apparatus that sequentially stacks a plurality of semiconductor chips while aligning the plurality of semiconductor chips on a stage. A condition determinator determines whether an apparatus performing a mounting processing stops during a mounting processing of the plurality of semiconductor chips. An evacuation controller evacuates, when it is determined that the apparatus performing the mounting processing stops, a group of semiconductor chips that has been stacked before the determination. A resuming determinator determines whether to resume the mounting processing after it is determined that the predetermined condition is satisfied. A return controller returns the evacuated group of semiconductor chips to a position before the evacuation and continues the mounting processing when it is determined that the mounting processing is resumed.

Abstract: A memory device includes a conductive layer, a plurality of first electrode layers, a first semiconductor layer extending through the plurality of first electrode layers in a first direction toward the plurality of first electrode layers from the conductive layer, a first insulating film including a tunneling insulator film, a charge-trapping film and a blocking insulator film, a second electrode layer, and a semiconductor base. The charge-trapping film is spaced along the first direction from the semiconductor base, a distance in the first direction between the charge-trapping film and the semiconductor base is larger than a thickness of the blocking insulator film in a second direction toward the plurality of first electrode layers from the first semiconductor layer.

Abstract: A method for manufacturing a semiconductor device includes forming a first source/drain region in a substrate. A core channel region is formed on the first source/drain region. A barrier layer is formed on the core channel region. A shell is formed lining sidewalls of the core channel region and sidewalls and top surface of the barrier layer. The shell includes a channel portion in contact with the core channel region and a barrier portion in contact with the barrier layer. A second source/drain region is formed above the shell. A first gate electrode is formed to surround the channel portion of the shell. A conduction energy band of the channel portion of the shell is aligned with a conduction energy band of the barrier portion of the shell.

Abstract: A display device is provided. The display device provides an electroluminescent display panel above the joint display panel. An orthographic projection of the electroluminescent layer on the joint display panel us overlapped with the edge frames of the display panel, and the electroluminescent layer includes multiple electroluminescent device. When the display device is operating, the multiple sub-display panels of the display panel and the multiple electroluminescent devices of the electroluminescent display panel can simultaneously emit a light in order to display an image in order to eliminate a black line generated by the edge frames of the joint display panel in order to increase the display effect to have a good product quality.

Abstract: The present application discloses a display substrate. The display substrate includes a base substrate; a plurality of thin film transistors for driving image display on the base substrate; a planarization layer on a side of the plurality of thin film transistors distal to the base substrate; and a pixel definition layer defining a plurality of subpixel regions. The display substrate includes a recess extending into the planarization layer and in an inter-subpixel region of the display substrate. The display substrate further includes a recess fill layer in the recess. The recess fill layer has a light transmittance rate lower than that of the planarization layer.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate comprises a base substrate and an anode, an organic light-emitting layer and a cathode formed on the base substrate sequentially, wherein the display substrate further comprises a plurality of functional patterns formed between the organic light-emitting layer and the anode, the plurality of functional patterns is divided into different types based on colors of a plurality of sub-pixels, and each type of the plurality of functional patterns is disposed in a region of the sub-pixel with a color corresponding to the type; the plurality of sub-pixels with different colors has different driving voltages, and a resistance value of each type of the plurality of the functional patterns in a direction perpendicular to the organic light-emitting layer is controlled to decrease as the driving voltage of the sub-pixel with the color corresponding to the type increases.

Abstract: A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor die, and a second semiconductor die. The first semiconductor dies includes high-density bumps and low-density bumps. The second semiconductor die includes high-density bumps and low-density bumps. The high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the high-density patch. The low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.

Abstract: Embodiments of the present invention include a tight pitch stack nanowire semiconductor device. The semiconductor device includes an active region including a blanket dielectric nanosheet. Further included are at least one fin formed on the blanket dielectric nanosheet. There is at least one gate structure formed over the at least one fin in the active region such that the blanket dielectric nanosheet forms an insulating layer between each of the at least one fin and the at least one gate structure, and a substrate such that each of the at least one fin and each of the at least one dummy gate are electrically isolated.

Abstract: A memory system having heat spreaders with different arrangements of projections are provided. In some embodiments, the memory system comprises a substrate, a first semiconductor device attached to a first side of the substrate, a second semiconductor device attached to a second side of the substrate, a first heat spreader attached to the first semiconductor device, and a second heat spreader attached to the second semiconductor device. The first heat spreader has a plurality of first projections facing a first direction and positioned in a first arrangement, and the second heat spreader has a plurality of second projections facing a second direction and positioned in a second arrangement different than the first arrangement. In some embodiments, the first projections are aligned with a majority of the second projections in a first direction and are offset with a majority of the second projections in a second direction.

Abstract: A power transistor is provided with at least one transistor finger that lies within a semiconductor material. The gate oxide is segmented into a set of segments with thick field oxide between each segment in order to reduce gate capacitance and thereby improve a resistance times gate charge figure of merit.

Abstract: In a trench-gate MOSFET, between a channel and an n+-type source region, an n-type shunt resistance region is provided in contact with the n+-type source region and the channel. The n+-type source region is disposed at a position separated from a gate insulating film at a side wall of a trench, in a direction parallel to a front surface of a semiconductor substrate. The n-type shunt resistance region is disposed, positioned deeper toward a drain electrode than is a front surface of the semiconductor substrate and shallower toward a source electrode than is the channel, and reaches a position deeper toward the drain electrode from the front surface of the semiconductor substrate than is the n+-type source region. The n-type shunt resistance region is a resistor for reducing current between the drain and the source when a large current exceeding a rated current flows during a short circuit.

Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a semiconductor element provided in the semiconductor substrate, the semiconductor element including a gate insulating film provided in the first plane, a first electrode provided on the first plane, a second electrode provided on the first electrode, the second electrode including a first metal material, the second electrode having a film thickness of (65 [g·?m·cm?3])/(density of the first metal material [g·cm?3]) or more, a first solder portion provided on the second electrode, a third electrode provided on the first solder portion, a fourth electrode provided on the first plane, a fifth electrode provided on the fourth electrode, the fifth electrode including a second metal material, the fifth electrode having a film thickness of (65 [g·?m·cm?3])/(density of the second metal material [g·cm?3]) or more, a second solder portion provided on the fifth electrode, and a sixth electrode pr

Abstract: The present disclosure relates to a quantum dot light-emitting diode, comprising: a first electrode layer, a hole transport layer, a quantum dot light-emitting layer, an electron transport layer, and a second electrode layer, which are sequentially formed on a base substrate; and a buffer layer arranged between the quantum dot light-emitting layer and the electron transport layer, wherein the buffer layer is configured such that a difference between an electron injection rate and a hole transport rate of the quantum dot light-emitting layer is less than a preset threshold. The present disclosure further relates to a method for preparing a quantum dot light-emitting diode, and an array substrate and a display device including the quantum dot light-emitting diode.

Abstract: Disclosed is a light emitting display device that can enhance light extraction efficiency of light which is emitted from a light emitting element. The light emitting display device includes an overcoating layer on a substrate and including a plurality of protruding portions, a first electrode on the plurality of protruding portions, a light emitting layer on the first electrode, and a second electrode on the light emitting layer. The first electrode has a contour which conforms to contour of the plurality of protruding portions. The light emitting layer has a contour different from the contours of the plurality of protruding portions.

Abstract: A display that includes a base layer having an emission area and a non-emission area adjacent to the emission area. A circuit element layer is disposed on the base layer. A display element layer is disposed on the circuit element layer. The display element layer includes an organic light emitting diode. An encapsulation layer is disposed on the display element layer and is configured to encapsulate the organic light emitting diode. A color filter layer is disposed in the encapsulation layer. The color filter layer includes a color shielding layer having a plurality of layers disposed in the non-emission area and a color filter disposed in the emission area.

Abstract: In a described example, a method includes: forming a metal layer on a backside surface of a semiconductor wafer, the semiconductor wafer having semiconductor dies spaced apart by scribe lanes on an active surface of the semiconductor wafer opposite the backside surface; forming a layer with a modulus greater than about 4000 MPa up to about 8000 MPa over the metal layer; mounting the backside of the semiconductor wafer on a first side of a dicing tape having an adhesive; cutting through the semiconductor wafer, the metal layer, and the layer with a modulus greater than about 4000 MPa up to about 8000 MPa along scribe lanes; separating the semiconductor dies from the semiconductor wafer and from one another by stretching the dicing tape, expanding the cuts in the semiconductor wafer along the scribe lanes between the semiconductor dies; and removing the separated semiconductor dies from the dicing tape.

Abstract: An integrated circuit structure is provided which comprises: a stack of source regions of a stack of transistors and a stack of drain regions of the stack of transistors; and a gate stack that forms gate regions for the stack of transistors, wherein the gate stack comprises traces of a first polymer of a block copolymer, the block copolymer comprising the first polymer and a second polymer.