Abstract: Methods and apparatuses for processing Satellite Positioning System (SPS) signals. In one exemplary method, a first set of frequency coefficients, which corresponds to a first Doppler frequency of an SPS signal, is determined, and said SPS signal is processed in a matched filter with the first set of frequency coefficients during a first window of time. A second set of frequency coefficients, which corresponds to a second Doppler frequency of the SPS signal, is determined, and the SPS signal is processed in the matched filter with the second set of frequency coefficients during a second window of time, where the first and second windows of time occur within a period of time which is not greater than one SPS frame period.

Abstract: A method for reducing DC offset from a receiver signal. The method includes jointly (i.e., simultaneously) estimating such DC offset and channel impulse response, and reducing the DC offset in accordance with the estimated DC offset and the estimate of the channel impulse response.

Abstract: An orthogonal demodulating section converts the frequency of received signals to the lower range in batch after rejecting an image band thereof by an RF filter. An image rejecting section rejects the image band of the orthogonally converted output. It allows an enough image rejecting degree to be obtained. An A/D converter section converts the whole range into a digital signal and an orthogonal demodulating section demodulates a desirable channel by means of digital processing. Then, a channel selecting section selects and outputs the desirable channel. It then allows wide-bands to be received in batch, flexible processing to be achieved by the digital processing and an enough image rejecting degree to be obtained.

Abstract: In a system having a received PN clock signal, a method is disclosed for providing a synchronized system clock signal having reduced jitter wherein the synchronized system clock signal is synchronized with the received PN clock signal. The method includes providing a stable high frequency reference signal and dividing the high frequency reference signal to provide a system clock signal having a plurality of system clock phases. The method also includes adjustably selecting a system clock phase of the plurality of system clock phases in accordance with the received PN signal in order to provide the synchronized system clock signal. The received PN clock signal is recovered by providing PN phase adjustments of the received PN clock signal. A tracking control signal is provided in accordance with the PN phase adjustments and the system clock phase is adjustably selected in accordance with the tracking control signal. The high frequency reference signal can be multiplied prior to the dividing.

Abstract: In order to transmit variable length encoded data in low signal to noise ratio environments, a first data pattern is added to a beginning portion of encoded data to signify a beginning of the encoded data. Further, a second data pattern is added to end portion of the encoded data to signify and end of the encoded data. Additionally, since the encoded data may naturally include the second data pattern and thereby mistakenly indicate an end of the encoded data, the encoded data is first checked for such a pattern. If the pattern is found within the encoded data, a new pattern is substituted therefore. In order to counter errors, patterns similar to the first data pattern are also substituted with new patterns. As such, a variable length encoded data can be transmitted in a low signal to noise ratio environment, and can thereafter be easily decoded.

Abstract: A method of transmitting information over POTS wiring includes transmitting a first delimiter signal, in the form of a multi-cycle waveform having a frequency of approximately 7.5 MHz, over the POTS wiring. A second delimiter signal, also comprising a multi-cycle waveform, is then later propagated over the POTS wiring. The time duration between the respective propagations of the first and second delimiter signals defines a symbol, which encodes information. The time duration is also such that reflections on the carrier medium resulting from the propagation of the first delimiter signal decay to a predetermined level prior to propagation of the second delimiter signal.

Abstract: A dual path equalizer for processing blocks of data includes first and second pre-processors, first and second finite filters, first and second post-processors, and an adder. The first pre-processor applies coefficients b1 to a received signal, the first finite filter applies coefficients a1 to an output of the first pre-processor in order to substantially eliminate a ghost from the received signal, and the first post-processor applies coefficients c1 to an output of the first finite filter. The second pre-processor applies coefficients b2 to the received signal, the second finite filter applies coefficients a2 to an output of the second pre-processor in order to substantially eliminate a ghost from the received signal, and the second post-processor applies coefficients c2 to an output of the second finite filter.

Abstract: An improved ADPCM encoding and decoding apparatus for compressing and de-compressing a differential signal between an input digital signal and a predicted value of said digitized input in accordance with adaptive differential pulse code modulation is described. The apparatus includes a prediction unit for receiving the previous differential signal and performs the prediction in accordance with one of a plurality of different algorithms which is selected by referring to the previous differential signal.

Abstract: A method for reducing the settling time in PLL circuits, particularly for use in an RF transceiver, the PLL circuits including a phase comparator, a filter, a digital-analog converter and an adder that are suitable to produce in output a voltage (VC) for controlling a voltage-controlled oscillator provided by means of a varactor, the method including determining the dependency of the control voltage (VC) of the voltage-controlled oscillator on the frequency of a selected channel of a transmitter; and generating a law describing the variation of the output current (IDAC) of the digital-analog converter such that the voltage (VDAC) obtained from the output current of the digital-analog converter, added to an output voltage (Vf) of said filter keeps the filter voltage (Vf) constant in order to reduce the settling time of the PLL circuit as a selected channel varies.

Abstract: In a data receiver, pulse edges are sequentially detected from the pulse string. If a pulse which has a width equal to two cycles of the reference clock signals is detected, bit data ‘1’ is restored. If two consecutive pulses each of which has a width equal to one cycle are detected, bit data ‘0’ is restored. If a pulse width between two consecutive pulse edges is not equal to one cycle or two cycles, it is presumed that a pulse edge of an erroneous pulse is detected. If the pulse width between the pulse edge, which is presumed to correspond to the erroneous pulse, and the next pulse edge is equal to or shorter than a predetermined threshold Th, the pulse edge and the next pulse edge is invalidated.

Abstract: An artificial ramping waveform profile is applied to a burst transmission power amplifier in order to reduce transients. A profile source is supplied with a plurality of pre-determined artificial ramping profiles. At the beginning of the burst transmission ramping period, one of the artificial ramping profiles is selected and fed to the power amplifier. The selection of the artificial ramping profile is based at least in part on the first message symbol of the message to be burst transmitted. Preferably, each different possible first message symbol has its own unique corresponding artificial ramping profile, and the corresponding waveform is used to artificially ramp the power amplifier when that message symbol is the first message symbol. At the end of the ramping period, the inputs to the power amplifier are switched to the traditional signal source, such as the FIR filters, etc., for receipt of the message symbols.

Abstract: A dual-frequency hopping device and method for a frequency synthesizer. An intermediate local oscillating frequency is decreased in the unit of a first frequency by a prescribed number of times as a channel is sequentially increased, to output an intermediate local oscillating frequency signal. A radio local oscillating frequency is increased by one level in the unit of a second frequency when the intermediate local oscillating frequency is decreased by the prescribed number of times, to output a radio local oscillating frequency signal.

Abstract: A digital signal processing architecture is disclosed which is operable to receive a spread-spectrum/CDMA signal and perform the despreading operation thereon. The quadrature and in-band components of the signal (rI, rQ) are received and stored in a memory. The digital signal processor is operable to execute a plurality of single instructions in a sequential manner, one for each instruction cycle. Each of these single instructions cause data to be extracted from the memory, processed and an output provided in the form of a despread signal (RI, RQ). The process is performed in response to the generation of the single instruction by placing in the data path a DSP process that will perform the despreading operation by performing various multiplications, summations, and accumulations, all in a single instruction cycle.

Abstract: An asynchronous timing oscillator re-synchronizer enables a clocked system which uses a high frequency clock to measure time intervals to re-synchronize to the clock after it has been temporarily disabled, using a low frequency, low accuracy, low power clock to determine the number of high frequency clock cycles that would have occurred during such intervals. Both high frequency and low frequency clocks are provided to the re-synchronizer, and the ratio between their respective frequencies is periodically determined and stored. A command sent to the re-synchronizer disables the high frequency clock for a specified number of cycles of the low frequency clock. When the disablement period has expired, the high frequency clock is re-enabled.

Abstract: A unit which processes multiple signals transmitted through utility wiring by receiver/LAN has a utility wiring connecting terminal (10) connected to the utility wiring by receiver/LAN, at least one input-output terminal for connecting computer (11) connected to the terminal (10), and at least one input-output terminal for connecting receiver (12) connected to the terminal (10). First signal interference preventing circuits (13 and 19) are respectively connected between the terminal (10) and the input-output terminal (12) so as to check the reverse flow of LAN signals. Therefore, signals for a television receiver, etc., and LAN signals can be transmitted through a coaxial cable for television, etc., wired in an already existing building without causing interference between the signals.

Abstract: An apparatus for and method for acquiring synchronization for use in communications systems, i.e., acquiring the presence of a packet of data and associated timing information. A sequence of symbols having known rotation and phase is transmitted to the receiver. The receiver attempts to match the received vectors in a predefined manner in order to determine whether a signal or noise is being received. CSK modulation is used for the synchronization acquisition stage and, any desired data carrying modulation may be switched to once synchronization is obtained, which may or may not be CSK. The transmitter transmits data in the form of packets to the receiver, wherein each packet is preceded by a preamble comprising a number of symbols. The length of the preamble can be any suitable number of symbols such that the receiver is able to synchronize with the transmitter. The preamble comprises a sequence of rotated or non-rotated symbols, inverted or non-inverted (or generally phase-rotated by some amount).

Abstract: A serial data receiver receives a serial data including first data defined as a judgment data indicative of at least one of a data reception rate and a reception data length. A shift register receives the serial data. The first data of the serial data received by the shift register is decoded by a decoder. The decoded result of the decoder is stored in a state register. A control circuit determines at least one of a data reception rate and a reception data length for the reception of the second and subsequent data of the serial data by the shift register based on the decoded result stored in the state register.

Abstract: The bandwidth of a ‘single loop’ bit synchronizer is maintained constant over a relatively wide baud rate range, by making the loop's phase/frequency detector gain constant proportional to the loop's clock divider ratio. The phase/frequency detector may include charge pump that charges a capacitor with a current representative of the phase/frequency difference between an input data signal and the clock signal produced by the loop's clock divider. By resistor-coupling the loop filter to the capacitor, the loop filter sees a voltage that is proportional to the integral of the phase/frequency detector's output current over the symbol period of the received data signal. Since the data symbol period is the inverse of the data rate, and corresponds to the ratio of the clock frequency divisor N to the fixed output frequency produced by the VCO, the gain constant of the phase detector is proportional to the clock divisor N.

Abstract: In a phase matching circuit for generating a system clock signal for an incoming data signal from a locally existing clock signal, a delay signal is calculated from the detected phase position of the data signal in that a memory addressed with the detected phase position outputs an allocated delay signal. In a specific embodiment, the memory is supplied with an address that is compensated by the most recently identified delay. In a further development, a control comprising the memory shares circuits for a number of data signals. The phase matching, which automatically recognizes a jitter compatibility more suitable for the clocking than the jitter compatibility employed at the moment, can be completely integrated and avoids circuit areas that are operated with a higher bit repetition rate than that of the clock signal.

Abstract: A shared data and clock recovery circuit including a clock synthesizer for generating sampling signals having different phases, a multiple transition detector for receiving a data stream and sampling signals, and for detecting edges in a data stream in response to the sampling signals, a counter and accumulator for detecting the time occurrences and total number of edges, and for performing weighted average calculation to select one of the phases, a decision circuit for detecting the phase difference between a source clock and a local clock such that if the PPM difference between the source clock and the local clock is at least 200 PPM, then selection of a phase is based upon stored historical information, and if the PPM difference between the source clock and the local clock is less than 200 PPM, then selection of a phase is based on a weighted averaging calculation.