Patents Examined by Duy Nguyen
  • Patent number: 8204254
    Abstract: An amplifier is provided using digital potentiometer integrated circuits to control the tone of a vacuum tube preamplifier allowing digital control of the analog signal path of the amplifier. Using digital potentiometer integrated circuits to control the tone of a vacuum tube preamplifier results in an amplifier that preserves the unique tone quality of a vacuum tube amplifier that offers the flexibility, versatility, and user-friendly features of a digitally controlled amplifier, such as the ability to save and recall amplifier settings. The amplifier of the present invention is especially applicable for use with musical instruments such as for example, electric guitars.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: June 19, 2012
    Inventor: Donelson Arthur Shannon
  • Patent number: 8202746
    Abstract: Provided is a method of manufacturing an LED package, the method including preparing a mold die which includes an upper surface and a lower surface having an outer circumferential surface and a concave surface surrounded by the outer circumferential surface, the mold die having an outlet extending from the upper surface to the lower surface; preparing a base having a light emitting section formed therein; forming an inlet formed in a predetermined region of the base excluding the region where the light emitting section is formed; positioning the mold die on the light emitting section; forming a mold member by injecting a molding compound into the inlet of the base; and removing the mold die.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: June 19, 2012
    Assignee: Samsung LED Co., Ltd.
    Inventors: Seon Goo Lee, Geun Chang Ryo, Dong Yeoul Lee, Yong Tae Kim, Young Jae Song
  • Patent number: 8199932
    Abstract: A signal processing apparatus includes a plurality of equalizers configured to input an audio signal of a corresponding channel among audio signals of a plurality of channels and configured to perform at least gain adjustment on the basis of a set parameter, each of the equalizers being provided in such a manner as to correspond to an audio signal of one of the plurality of channels; a plurality of output sections configured to output each audio signal for each of the plurality of channels, the audio signal being processed by the equalizer; a measurement section configured to measure frequency-amplitude characteristics of the audio signal output from the output section; and a computation section configured to perform a computation process for correcting frequency-amplitude characteristics of an audio signal of each channel on the basis of the measurement result by the measurement section.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: June 12, 2012
    Assignee: Sony Corporation
    Inventor: Kenji Nakano
  • Patent number: 8180071
    Abstract: A multiplier 3 multiplies a square wave signal A(?,t) by a low frequency component signal L(?,t) to generate an even-order harmonic component signal B(?,t). A multiplier 4 multiplies the even-order harmonic component signal B(?,t) by the low frequency component signal L(?,t) to generate an odd-order harmonic component signal C(?,t). An adder 5 adds the even-order harmonic component signal B(?,t) and the odd-order harmonic component signal C(?,t) to generate the harmonic component signal D(?,t).
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: May 15, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takashi Yamazaki, Masaru Kimura
  • Patent number: 8173453
    Abstract: Patterning an organic light emitting diode (OLED) after it has been encapsulated by permanently changing the light emissivity of the diodes. The OLED includes an intervening layer between a source of laser treatment and a light emitting layer. Depending on the composition of the light emitting layer, the laser treatment will enhance or diminish brightness.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: May 8, 2012
    Assignee: 3M Innovative Properties Company
    Inventors: Fred B. McCormick, Robert C. Fitzer, Hung T. Tran
  • Patent number: 8164157
    Abstract: This patent pertains to a new technique of increasing the amount of energy absorbed by an antenna. It accomplishes this by broadcasting a spike that attracts the signal when the fields of its oscillating charge are at their strongest.
    Type: Grant
    Filed: July 27, 2008
    Date of Patent: April 24, 2012
    Inventor: David Robert Morgan
  • Patent number: 8158514
    Abstract: The invention relates to a method for producing vertical electrical connections in semiconductor wafers, the method including the following steps: application of a protective resist to the wafer front side; patterning of the protective resist such that the contacts to be connected to the wafer rear side become free; laser drilling of passage holes at the contact connection locations from the wafer rear side through the semiconductor substrate, the active layers and the contacts to be connected on the wafer front side; cleaning of the wafer; application of a plating base to the wafer rear side and into the laser-drilled passage holes; application of gold by electrodeposition onto the metallized wafer rear side and the passage holes; resist stripping of the protective resist; and application of an antiwetting layer in the region of the entrance openings of the passage holes at the wafer rear side.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: April 17, 2012
    Assignee: Forschungsverbund Berlin E.V.
    Inventors: Olaf Krüger, Joachim Würfl, Gerd Schöne
  • Patent number: 8150070
    Abstract: A bass and treble audio tone control circuit configured as an integrated circuit, wherein a capacitor for setting a frequency band can be accommodated in an integrated circuit. A LPF extracts a low sound region component SLO from an initial sound signal SIN. A low sound region adjustment circuit adjusts the gain of SLO and generates signal SLT. An inverting circuit inverts SLO and an adding circuit extracts a high sound region component SHO by adding the inverted SLO and SIN. A high sound region adjustment circuit adjusts the gain of SHO and generates a signal SHT. A synthesizing circuit synthesizes SIN with SHT and SLT, and generates an output sound signal SOUT. The LPF is composed of an RC active filter, and the resistance that establishes the cutoff frequency is composed of an equivalent resistance using a switched capacitor circuit.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: April 3, 2012
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventor: Tomoki Shioda
  • Patent number: 8139789
    Abstract: A plurality of main amplifiers amplifies input audio signals with an adjustable gain. A first selector selects any of the input audio signals. An auxiliary amplifier receives an output of the first selector and amplifies this output with an adjustable gain. A second selector receives n outputs from the main amplifiers and selects any of the outputs. A soft switching circuit receives an output of the second selector at a first input terminal, receives an output of the auxiliary amplifier at a second input terminal, and makes the output transition gradually from one of the input terminals to the other of the input terminals. Output switches are respectively provided for the main amplifiers, an output of a corresponding main amplifier is received at a first input terminal, an output of the soft switching circuit is received at a second input terminal, and one of the outputs is selected to be outputted.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: March 20, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Mitsuteru Sakai, Yosuke Sato
  • Patent number: 8119547
    Abstract: A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-charge-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port and a treatment section. The static-charge-eliminated semiconductor substrate is accommodated in the container positioned to the load port. Thus, it is possible to decrease foreign materials adhering to the semiconductor substrate and errors in handling the semiconductor substrate.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: February 21, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiaki Kobayashi
  • Patent number: 8106417
    Abstract: A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal techniques. Trenches that define the boundaries of the individual devices are formed through the semiconductor layers and into the insulating substrate, beneficially by inductive coupled plasma reactive ion etching. A first support structure is attached to the semiconductor layers. The hard substrate is then removed, beneficially by laser lift off. A second supporting structure, preferably conductive, is substituted for the hard substrate and the first supporting structure is removed. Individual devices are then diced, beneficially by etching through the second supporting structure. A protective photo-resist layer can protect the semiconductor layers from the attachment of the first support structure.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: January 31, 2012
    Assignee: LG Electronics Inc.
    Inventor: Myung Cheol Yoo
  • Patent number: 8101494
    Abstract: A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: January 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: David S. Collins, Kai D. Feng, Zhong-Xiang He, Peter J. Lindgren, Robert M. Rassel
  • Patent number: 8039358
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a trench on a semiconductor substrate to define a first and a second element regions; burying a first oxide film in the trench; forming a second oxide film on surfaces of the first and second element regions; performing a first ion doping using a first mask which is exposing a first region containing the first element region and a part of the first oxide; performing a second ion doping using a second mask which is exposing a second region containing the second element region and a part of the first oxide film; and removing the second oxide film formed in the first element region and the second element region by etching, and the first oxide film is selectively thinned using the first or second mask after performing the first or second ion doping.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: October 18, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masanori Terahara, Masaki Nakagawa
  • Patent number: 8026585
    Abstract: A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second conductive via pass through the die. The first conductive via has a first pad and a second pad, and the second conductive via has a third pad and a fourth pad. A fifth pad is conducted to the third pad. A sixth pad is conducted to the second pad. A seventh pad is conducted to the first pad. An eighth pad is conducted to the fourth pad. In a vertical direction of the die, the first pad and the second pad are overlapped, the third pad and the fourth pad are overlapped, the fifth pad and the sixth pad are overlapped, and the eighth pad and the seventh pad are overlapped, partially or totally.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: September 27, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Fa Chou, Ding-Ming Kwai