Patents Examined by E. S. Jackmun
  • Patent number: 4028880
    Abstract: An electronic timepiece powered during use by a cell comprises an oscillating circuit for generating a high frequency output signal and a multi-stage divider circuit for receiving the high frequency output signal and dividing it at successive stages to lower frequency output signals and providing at its last stage standard pulses suitable as a time standard. A first gate circuit receives the divided signals and gates therethrough higher frequency pulses than that of the standard pulses. A control pulse generating circuit generates a given number of control pulses having a predetermined pulse width in successive predetermined periods, and a second gate circuit receives at its input both the higher frequency pulses and the control pulses and gates therethrough a number of higher frequency pulses corresponding in number to the predetermined period within the duration of the predetermined pulse width.
    Type: Grant
    Filed: December 19, 1975
    Date of Patent: June 14, 1977
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventor: Takashi Ueda