Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes: receiving a substrate; forming a transistor surrounded by a dielectric layer over the substrate, wherein the dielectric layer includes a through hole, and the transistor is formed in the through hole; forming a gate contact in the through hole to electrically connect the transistor; forming a ferroelectric layer over the gate contact in the through hole; forming an insulating layer conformal to and over the dielectric layer and the ferroelectric layer; removing a portion of the insulating layer to form a spacer in the through hole and over the ferroelectric layer; and forming a top electrode over the ferroelectric layer and between the spacer.
Type:
Grant
Filed:
May 20, 2022
Date of Patent:
May 28, 2024
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Inventors:
Chih-Yu Chang, Sai-Hooi Yeong, Yu-Ming Lin, Chih-Hao Wang