Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.

Abstract: A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, a gate structure, a plurality of source/drain structures, a shallow trench isolation (STI) oxide, and a dielectric layer. The first semiconductor fin extends upwardly from the substrate. The second semiconductor fin extends upwardly from the substrate. The gate structure extends across the first and second semiconductor fins. The source/drain structures are on the first and second semiconductor fins. The STI oxide extends continuously between the first and second semiconductor fins and has a U-shaped profile when viewed in a cross section taken along a lengthwise direction of the gate structure. The dielectric layer is partially embedded in the STI oxide and has a U-shaped profile when viewed in the cross section taken along the lengthwise direction of the gate structure.

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

Abstract: Discussed is a tandem solar cell manufacturing method including etching a crystalline silicon substrate, whereby a solar cell can be obtained which does not have a pyramid-shaped defect on a surface of the substrate, inhibits the generation of a shunt through the substrate having excellent surface roughness properties, and can secure fill factor properties, the solar cell being capable of being obtained through the tandem solar cell manufacturing method. The method includes preparing a crystalline silicon substrate; performing an isotropic etching process of the substrate; and removing a saw damage on a surface of the substrate by performing an anisotropic etching process of the isotropically etched substrate.

Abstract: A photonic device manufacturing method, including a step of transfer, onto a same surface of a photonic circuit previously formed inside and on top of a first substrate, of at least a first die made up of a III-V semiconductor material and of at least a second die made up of silicon nitride, the method further including a step of forming of photonic components in said at least one first and at least one second dies.

Abstract: A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodetectors used with a broadband signal and methods of manufacture. The structure includes: a first photodetector; a second photodetector adjacent to the first photodetector; a first airgap of a first size under the first photodetector structured to detect a first wavelength of light; and a second airgap of a second size under the second photodetector structured to detect a second wavelength of light.

Abstract: Semiconductor devices and methods for forming the semiconductor devices include forming a sacrificial layer on a substrate on each side of a stack of nanosheets, the stack of nanosheets including first nanosheets and second nanosheets stacked in alternating fashion with a dummy gate structure formed thereon. Source and drain regions are grown on from the sacrificial layer and from ends of the second nanosheets to form source and drain regions in contact with each side of the stack of nanosheets. The sacrificial layer is removed. An interlevel dielectric is deposited around the source and drain regions to fill between the source and drain regions and the substrate.

Abstract: Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts.

Abstract: The invention relates to a method for improving the ohmic-contact behaviour between a contact grid and an emitter layer of a silicon solar cell. The object of the invention is to propose a method for improving the ohmic-contact behaviour between a contact grid and an emitter layer of a silicon solar cell, in which the effects on materials caused by irradiation of the sun-facing side are further minimized. In addition, the method should also be applicable to silicon solar cells in which the emitter layer has a high sheet resistance.

Abstract: A packaging structure is provided. The packaging structure includes a plurality of first chips; and a molding layer between adjacent first chips. The molding layer covers a sidewall of the first chip and exposes a top surface of the first chip.

Abstract: A method is provided for producing a microelectronic device having a subsequent grating of reliefs of which at least one wall is slanted, the method including providing a structure including a base, and an initial grating of reliefs, each relief having at least one proximal end in contact with the base, a distal end, and at least one wall extending between the proximal end and the distal end; and laying the reliefs of the initial grating on one another, by application of at least one stress on the structure, such that walls facing two adjacent reliefs come into contact, thus generating at least one subsequent grating of reliefs of which at least one wall is slanted.

Abstract: A method of forming an area of electric contact with a semiconductor region mainly made of germanium, comprising the forming of a first area made of a first intermetallic material where more than 70% of the non-metal atoms are silicon atoms. There is also described a device including such a contacting area.

Abstract: The production process according to the invention consists of a nanometric scale transformation of the crystalline silicon in a hybrid arrangement buried within the crystal lattice of a silicon wafer, to improve the efficiency of the conversion of light into electricity, by means of hot electrons. All the parameters, procedures and steps involved in manufacturing giant photoconversion cells have been tested and validated separately, by producing twenty series of test devices. An example of the technology consists of manufacturing a conventional crystalline silicon photovoltaic cell with a single collection junction and completing the device thus obtained by an amorphizing ion implantation followed by a post-implantation thermal treatment.

Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

Abstract: A method for removing an undesired coating from a front face of a crystalline silicon solar cell includes: S1: depositing an Al2O3 film, an SiO2 film, and an SiNx film on a back face of a silicon wafer to form a backside passivation film, and forming an undesired coating on an edge of the front face of the silicon wafer; S2: preparing an aqueous film on a surface of the backside passivation film of the product obtained in S1; S3: passing the product obtained in S2 through an acid tank to remove the undesired coating; S4: passing the product obtained in S3 through a water tank to remove a residual treatment solution; and S5: drying the product obtained in S4.

Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.