Abstract: A quantum well (QW) layer is provided in a semiconductive device. The QW layer is provided with a beryllium-doped halo layer in a barrier structure below the QW layer. The semiconductive device includes InGaAs bottom and top barrier layers respectively below and above the QW layer. The semiconductive device also includes a high-k gate dielectric layer that sits on the InP spacer first layer in a gate recess. A process of forming the QW layer includes using an off-cut semiconductive substrate.
Type:
Grant
Filed:
February 20, 2009
Date of Patent:
February 14, 2012
Assignee:
Intel Corporation
Inventors:
Ravi Pillarisetty, Titash Rakshit, Mantu Hudait, Marko Radosavljevic, Gilbert Dewey, Benjamin Chu-Kung
Abstract: A stacked chip semiconductor device whose size is substantially reduced by high density packaging of two or more semiconductor chips. In the semiconductor device, four semiconductor chips are stacked over a printed wiring board. The bottom semiconductor chip has an interface circuit which includes a buffer and an electrostatic discharge protection circuit. All signals that these semiconductor chips receive and send are inputted or outputted through the interface circuit of the bottom semiconductor chip. Since the other semiconductor chips require no interface circuit, the semiconductor device is compact.
Abstract: Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.
Type:
Grant
Filed:
June 24, 2005
Date of Patent:
August 19, 2008
Assignee:
International Business Machines Corporation
Inventors:
David Ross Greenberg, John Joseph Pekarik, Jorg Scholvin
Abstract: The present invention relates to a multi-bit non-volatile memory device having a dual gate employing local charge trap and method of manufacturing the same, and an operating method for a multi-bit cell operation.
Type:
Grant
Filed:
April 21, 2006
Date of Patent:
July 22, 2008
Assignee:
Korea Advanced Institute of Science and Technology
Abstract: A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device.