Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices at their desired optimal speeds. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks.

Abstract: Information about the effects of calling each entry point in a program and information about external calls made by the program are recorded in an image information file. In addition to the addresses of the entry points and call destinations, the information may include any callback parameters and register usage associated with the entry points, and any definite values passed by the calls. When translating two separate but mutually dependent programs that are not easily merged for simultaneous translation, the image information files for the respective programs permit the programs to be alternately translated with rapid convergence by an iterative method of checked assumptions and re-translation.

Abstract: A process and apparatus for preparing said process for reducing the power consumption of microprocessor-based devices by reducing the frequency of the oscillator governing the logical operation of the microprocessor during periods of use in which system performance is not critical. In one embodiment of apparatus the microprocessor is controlled by a monitor circuit operable with the microprocessor and operated by the variable frequency oscillator. In another embodiment a hardware monitor circuit is utilized and which tracks microprocessor instructions to determine periods of use when performance is not critical. The shift in oscillator speed is mediated by a flip-flop latch circuit connected between one or more clock oscillators and the oscillator input of the controlled microprocessor.