Abstract: An apparatus and method of detecting a transmission code from a received signal, where the transmission code is composed of a plurality of dithered codes. The codes can be dithered either by varying the length of the code or varying the phase of the code according to a dither pattern and can be a stationary dither pattern that is fixed and generally known. The method includes detecting the plurality of dithered codes, and detecting the long code based on the detected dithered codes. A detection signal is generated for each detected dither code, the detection signals are combined, and the long code is detected based on the combination of detection signals. If the composite code includes M dithered codes, the correlation signals are combined by summing the M correlation sums to generate a present final sum.

Abstract: A multipath mitigation method consists of locating a multipath-invariant (MPI) point of an ideal autocorrelation function and measuring the distance between the MPI point and DLL. The same MPI point is located in a received correlation function, and the distance between the point and the DLL, now affected by multipath, is measured. The difference between the ideal distance and the actual distance is the code tracking error resulting from multipath. The error is subtracted from the computed pseudorange or used to control the DLL. The method can be used to reduce the effects of all types of tracking error sources, such as signal transmission failure or code noise.

Abstract: A synchronizing circuit synchronizes a predetermined code with first and second codes different in phase, include: a code generating part outputting phase-shifted code shifted in phase by a predetermined number of chips from the predetermined code; a first correlation detecting part detecting a correlation between the phase-shifted code from the code generating part and the first code; a second correlation detecting part detecting a correlation between the phase-shifted code from the code generating part and the second code; and a code shifting part shifting the phase of the phase-shifted code from the code generating part by a predetermined number of chips according to the detection results of the first and second correlation detecting parts.

Abstract: A circuit and method for controlling a spread spectrum transition are presented comprising a first circuit and a second circuit. The first circuit may be configured to generate a clock signal in response to (i) a reference signal, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal. The second circuit may be configured to synchronize the command signal to a feedback signal. The sequence of spread spectrum ROM codes may be generated according to a predetermined mathematical formula and optimized in accordance with predetermined criteria.

Abstract: A method of channel estimation in a Code Division Multiple Access (CDMA) transmission system that incorporates Pilot Symbol Assisted Modulation (PSAM) using an iterative coherent detection method to estimate the phase and frequency of the received pilot symbols. Arctangent calculations are used to estimate phase and frequency. An iterative least squares linearization identifies and corrects values of the arctangent associated with an incorrect 2? alias, which arise due to the multiple-valued nature of the arctangent function. An alternative non-iterative least squares linearization also corrects the arctangent values, based on a calculation involving stored values of the pilot symbols.

Abstract: A receiver is equipped with a demodulation circuit for taking a signal indicating broadcast contents of an analog broadcast out of the first and second intermediate-frequency signals, and for taking a signal indicating broadcast contents of a digital broadcast out of the first and second intermediate-frequency signals. Frequencies of local oscillation signals are made to be a first frequency within a frequency band of the digital broadcast adjacent to a frequency band of the analog broadcast received by the receiver at a time of receiving the analog broadcast, and the frequencies of the local oscillation signals are made to be a second frequency equal to the carrier frequency of the analog broadcast adjacent to the frequency band of the digital broadcast received by the receiver at a time of receiving the digital broadcast.

Abstract: A synchronized communication system for communicating signals into and from a medium is disclosed. The communication system utilizes a transmitter located at a central station external to the medium, which transmits a low frequency synchronization signal into the medium. Transceivers located within the medium receive the low frequency synchronization signal and send information radio signals synchronized with the low frequency synchronization signal to a receiver located at the central station. Zone transceivers are located within the medium to receive and retransmit the synchronization signal at the low frequency within a zone. The zone transceivers also receive information signals from transceivers in the zone and transmit zone information radio signals to the central station containing information corresponding to the information received from the transceivers in the zone.

Abstract: Architecture of an efficient adaptive digital echo canceller includes a frequency domain update block, a far-end signal estimation block and a time domain echo cancellation block. The echo canceller has a training mode in which the frequency domain update block and far-end signal estimation block are first trained to estimate the echo channel and target channel. After the training mode, the time domain echo cancellation block uses the estimated echo channel to synthesize an echo replica and subtracted it from the received signal continuously before or in an operation mode. When a synchronization frame is received in the operation mode, the frequency domain update block and the far-end signal estimation block are used to retune both echo channel and target channel for improving system performance.

Abstract: A spread-spectrum communication system utilizes spreading code sequences, which can be expressed as a matrix. The matrix of code sequences has or can be transformed to have a certain orthogonal relationship. In accord with the invention, a matched filter bank in a spread-spectrum receiver processes input signals that purport to contain the code matrix using two halves of an input stream matrix and only two of four possible quadrants of the code matrix as the reference inputs. Such processing produces two quadrants of a correlation signal matrix. It is then possible to determine the other two quadrants of the full correlation signal matrix from the known relationship with the two quadrants derived from the matching operations. The processing of only two of the quadrants of the signal matrix substantially reduces the number of computations and the amount of processor hardware needed to implement a matched filter bank to recognize the codes embedded in a received spread-spectrum signal.

Abstract: An apparatus and process for updating a sample time in a serial link which converts serial data in parallel data. A delay line stores multiple samples of at least two data bits received over the serial link. The contents of the delay line are matched so that they can be analyzed by a processor to determine an optimum sampling position in the delay line. The processor is programmed to analyze contents of the latch by creating a sample mask from a plurality of delay line samples. The sample mask identifies transition edges of first and second data bits within the delay line. The transition edges are validated with respect to the presence, for first and second initial sampling positions for the respective data bits. New sampling positions are determined from the validated edges, and the initial sampling positions are updated with sampling positions which have been determined from the new sampling positions.

Abstract: A positioning or timing receiver, for receiving pseudo-noise encoded signals includes mask mixers in the main signal paths, prior to accumulators. The mask mixers are fed with mask signals having a period equal to the period of the pseudo-noise code, provided by a mask generator. The mask generator and mixers provide an extra level of functionality in the receiver, through which a large number of uses can be made. For example, without modifying a code signal mixed into the main signal path, the mask mixers allow dynamic adaptability from a wide correlator to a narrow correlator by simple control of the mask generator. Many different discrimination patterns can be obtained. By changing the mask signals and examining correlator outputs, it is possible to detect whether a signal being tracked contains a multipath component. The receiver also includes a switch, whereby two correlators may be fed with signals from the in-phase main signal path.

Abstract: A method and apparatus to accelerate the evaluation of complex, computationally intense digital signal processing algorithms is disclosed. In one embodiment, a filter accelerator is connected in parallel with a conventional digital signal processor (DSP). The accelerator enhances the speed at which the DSP performs some filtering operations by calculating and maintaining a number of partial results based on a selected number of prior data samples. Each time the DSP receives a new data sample for filtering, the DSP makes use of one or more partial results from the accelerator to speed the calculation of the filtered result. Receipt of the new data sample causes the accelerator to recalculate the partial results, this time using the new data sample. The accelerator thus prepares for receipt of the subsequent data sample, freeing the DSP to perform other operations.

Abstract: A method of determining a current trellis describing a plurality of paths starting from an initial state, the paths having a predetermined length smaller than or equal to a maximum length, consists of storing a reference trellis comprising all the paths of the trellis of maximum length, extracting the paths of the current trellis from the reference trellis, taking into account the maximum length, the length of the current trellis, and the initial state of the paths.

Abstract: The amount of data transmitted in a primary data channel is increased by modulating a reference clock signal of the primary data channel with secondary data to form a separate secondary data channel. Primary data is formed into a primary data signal using the modulated reference clock signal, and a transmitter transmits the primary data signal to a receiver. The receiver recovers the primary data and modulated reference clock signal from the primary data signal, and then recovers the secondary data from the recovered modulated reference clock signal.

Abstract: A method is presented for implementing synchronization between the timing of a first telecommunication system and the timing of a second telecommunication system. A first counter value is regularly updated at a pace determined by the first telecommunication system and a second counter value is regularly updated at a pace determined by the second telecommunication system. At a first time instant the current first counter value is stored. At a second, later time instant the stored counter value is read. Using the read counter value an operational step is timed so that its timing in relation to the timing of the first telecommunication system is known.

Abstract: A system and method of preventing metastability in conjunction with the receipt in a first clock domain of an asynchronous digital signal from a second clock domain when the first domain operates with a first clock frequency, and the second domain operates with a second clock frequency that is known within the first domain. The first domain sends information to the second domain, and includes a reference signal containing phase information known in the first domain. The information is clocked into the second domain utilizing the reference information. The second domain then sends the asynchronous digital signal to the first clock domain. A receiving unit in the first domain determines the phase information from the received signal with a known degree of maximum uncertainty that is less than one period of the reference signal. The first domain then stably reads the received asynchronous digital signal.

Abstract: A plurality of target values for generating a gain control signal are provided such that switching is performed between the target values with a baseband signal processing unit. Specifically, the baseband signal processing unit monitors the state of a received signal to select an appropriate one of the target values based on the monitoring result. The selected target value is compared with a received power amount to generate the gain control signal. When saturation occurs at input ends of A/D converters for digital processing of the received signal, the target value is switched to the next lower target value. Thus, even when the received signal includes an interference wave in addition to a desired wave, saturation at the input ends of the A/D converters due to the interference wave is prevented, thereby making it possible to maintain favorable reception characteristics and suppression of an increased bit error rate in digital communication.

Abstract: The present invention provides an apparatus and method for code group identification and frame synchronization for cell searching used in wide-band DS-CDMA cellular systems. This method characterizes each secondary synchronization code sequence (SSCS) with a corresponding theoretical frequency sequence, which represents the occurrence times of CS1 to CS16 in a corresponding SSCS. Thus, 64 secondary synchronization code sequences corresponding to 64 code groups defined in DS-CDMA systems also corresponds to 64 theoretical frequency sequences. By characterizing the SSCS transmitted by a base station, a real frequency sequence can be generated. Comparing the real frequency sequence with the 64 theoretical frequency sequences, one can determine one or two candidate code groups, which may be employed by the base station.

Abstract: A data transmission method, particularly in electric networks, in which coded data are blockwise modulated onto several carrier frequencies within one or several particular frequency bands by an orthogonal frequency division multiplex method (OFDM) and in which the signal corresponding to a data block and obtained by inverse Fourier transformation is transferred to a receiver for a predetermined time duration (T), where individual signals succeed as signal blocks in time. In some embodiments, each signal is multiplied with a window function before transmission, the absolute value of the Fourier transform of which has a zero crossing at the respectively used carrier frequencies, and has secondary maxima, which have a damping of at least −30 dB in relation to the main maximum. In some embodiments, a digital filter can be used instead of the window function, the digital filter having an odd number of coefficients Ck, k=−m, . . . 0, . . .

Abstract: A novel design of, and method of operation for, a coherent delay lock loop (DLL) for communication systems that employ a pilot channel or pilot symbols is disclosed. Pilot information is used to produce an estimate of signal phase and thereby remove the need for the magnitude operation within the DLL arms. The disclosed design and method afford better time-tracking performance by avoiding the squaring loss (due to the magnitude operation) encountered in noncoherent DLL designs. Alternative embodiments disclose designs and methods that are robust to signal amplitude variation. A first alternative normalizes a DLL error signal by a computed estimate of the squared magnitude of the pilot signal. A second alternative normalizes the error signal using only the early and late signals and therefore is applicable for noncoherent DLL designs as well as coherent DLL designs.