Patents Examined by Edward Cudek, Jr.
  • System, method, and apparatus for a cache flush of a range of pages and TLB invalidation of a range of entries
    Patent number: 8214598
    Abstract: Systems, methods, and apparatus for performing the flushing of a plurality of cache lines and/or the invalidation of a plurality of translation look-aside buffer (TLB) entries is described. In one such method, for flushing a plurality of cache lines of a processor a single instruction including a first field that indicates that the plurality of cache lines of the processor are to be flushed and in response to the single instruction, flushing the plurality of cache lines of the processor.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: July 3, 2012
    Assignee: Intel Corporation
    Inventors: Martin G. Dixon, Scott D. Rodgers