Abstract: A floating gate is utilized which has two portions. A first portion overlies the channel region formed between the source and drain. The control gate overlies this portion of the floating gate and the remaining portion of the channel region forming an enhancement transistor. The second portion of the floating gate extends from the first portion over a thin oxide tunnel area of the source. An additional diode implant forming a junction with the drain region is provided to regulate the current flow through the drain, particularly during erasure.

Abstract: A metal lead frame for an integrated circuit package is disclosed having stress relieving means formed therein to inhibit breakage of a thermally mismatched silicon die subsequently attached thereto and then heated during normal operation of the device. The stress relieving means may comprise parallel grooves formed in one or both surfaces of the central portion of the lead frame where a silicon integrated circuit die will subsequently be bonded to the lead frame. Preferably, the grooves are formed in both axes comprising the plane of the lead frame and may be formed on both surfaces of the lead frame. The stress relieving means may also comprise a series of openings cut through the central portion of the lead frame.

Abstract: A P-well region is provided in a semiconductor substrate of N-type. A P-channel MOSFET is arranged in the N-type substrate while an N-channel MOSFET is arranged in the P-well region. The drain regions of the respective MOSFETs consist of high concentration impurity diffused regions and low concentration impurity diffused regions arranged about the respective high concentration impurity diffused regions. Also, a drain electrode is provided to cover the entire of the high and low concentration impurity diffused regions.

Abstract: A CMOS semiconductor integrated circuit device has an n-(p-)MOS element formed on a p-(n-)type semiconductor substrate and a p-(n-)MOS element formed on an n-(p-)type well region. A substrate potential wiring for providing a substrate potential to the p-(n-)type semiconductor substrate and a source potential wiring connected to the source region of the n-(p-)MOS are provided physically independently from each other, and such potential wiring and such source potential wiring are connected with each other with a resistor being interposed therebetween. Thus, the current which flows in transistors during the operating state of related circuits integrated in the substrate is prevented from flowing into the substrate thereby eliminating any such fluctuations of the substrate potential as may otherwise be caused by the operation of the circuits.

Abstract: The described embodiments of the present invention show a structure and process for fabricating this structure in which a bi-stable logic device, such as a static random access memory cell, is formed. The advantages of the described embodiments are most particularly found when in an array. In two parrallel lines formed in buried diffusions beneath the surface of the integrated circuit, V.sub.dd or the power supply voltage and ground are alternately provided. Two vertical transistors control conduction between ground and a surface diffusion are formed being connected to the buried ground diffusion. Two additional transistors are formed as load devices connected between the surface diffusion and the V.sub.dd buried diffusion. The surface diffusion is connected to complementary bit lines via access transistors formed connecting the surface diffusion to contact points for the complementary bit lines. By using buried ground and supply lines, large space savings may be obtained with the present memory cell.

Abstract: In a process for fabricating a bipolar transistor with a single polysilicon layer, a silicon nitride layer 22 and a phospho-silicate glass layer 24 are formed on top of the polysilicon layer and the link oxide layers. The glass layer 24 has a high etch selectivity compared to the nitride layer 22 so that the glass layer may be overetched above the emitter polysilicon region without overetching the link oxide. The nitride layer is then removed by etching without significantly affecting the link oxide layer. Thus the emitter metal contact may be self-aligned on top of the emitter polysilicon region 14, 114.

Abstract: A gate-drain shield is used to reduce the gate to drain capacitance of a transistor. The gate-drain shield is formed as a conductor that is positioned on the surface of the transistor between the gate and the drain. The conductor is formed on an insulator thereby electrically insulating the conductor from the substrate of the transistor.

Abstract: A P- semiconductor material substrate which has been ion-implanted with N-type dopants to form an N+ subcollector layer is annealed in Argon to further remove implant damage and drive the dopant ions deeper into the P substrate. Next a lightly doped N- epitaxial layer is grown on the N+ subcollector layer. This forms the blanket collector. A P- well region is formed by growing a pad oxide of 10 nm on the N-epi layer and a 200 nm layer of nitride is then deposited on top of the layer oxide. A photoresist etch mask is used to pattern the P- well region. A reactive ion etch is performed through the dielectric oxide and nitride layers, through the epitaxial layer and stopping in the subcollector layer. A layer of low temperature expitaxial material is grown over the structure using ultra-high vacuum/chemical vapor depositions such that the epitaxial layer extends above the surface of the epitaxial layer and includes a P+ heavily doped layer and a lightly P-doped surface layer.

Abstract: A lateral DMOSFET device with a small on resistance and a small device area.

Abstract: A method for forming a contact in a semiconductor integrated circuit includes the formation of a conformal oxide layer over the device followed by formation of a doped glass layer. The integrated circuit is heated to cause the glass layer to reflow, improving planarity of the circuit. A second conformal oxide layer is then formed, and contact vias are cut through the three part interlevel dielectric layer. Side walls are then formed in the via by depositing a third conformal layer, and anisotropically etching such layer. This isolates the doped reflowable glass layer from the via. Metal interconnect can then be deposited and defined, forming a contact in the via.

Abstract: A method for manufacturing a self-aligned contact MOS field effect transistor integrated circuit has a substrate doped with a first conductivity. The substrate has field oxide regions separating the planned active transistor regions, and gate dielectric/gate electrode structures over the designated channel regions for the integrated circuit device. Opposite type conductivity ions are implanted into the doped silicon substrate to form the lightly doped portion of the source/drain regions for the transistor. Dielectric spacers are formed on the sidewalls of the dielectric/gate electrode structures. A block out mask is formed over the source/drain regions designated to have self-aligned contacts made thereto. Opposite type conductivity ions are implanted into the substrate to form heavily doped portions to complete the formation of the source/drain regions in those nondesignated self-aligned contact regions. The block out mask is removed.

Abstract: The described embodiments of the present invention provide DRAM cells, structures and manufacturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. In another embodiment of the present invention, a planar capacitor is used with a field plate isolation scheme including a transfer transistor moat region self-aligned to the field plate. This structure allows the elimination of alignment tolerances between the capacitor and the transistor thus reducing the space necessary between the transistor and the capacitor.In another embodiment of the present invention, a memory cell using two conductive plates formed inside a trench as the storage capacitor is fabricated.

Abstract: Disclosed is a method for manufacturing a high-denisty multilayer metallization pattern on an integrated circuit structure. Also disclosed are integrated circuit structures made with such method. The components of the integrated circuit may be formed on the substrate using conventional processes. A first metallization pattern is then formed on the semiconductor substrate having at least one integrated circuit. Next, the first layer of a double-layer insulation is applied over the first metallization pattern, and a photoresist layer is applied over the first layer for planarizing the topology of the metallization pattern and for defining a pad mask by a photoprocess over a conductive pad. For planarization of the topology, the photoresist layer and the first layer of the double-layer insulation are reactive ion etched at substantially the same rate to a desired depth. This reactive ion etching step also removes the first layer of the double-layer insulation from the pad mask area thereby exposing a metal pad.

Abstract: A complementary MISFET uses gallium antimonide as the active material to utilize the high mobilities of both holes and electrons in such material. To avoid interfacial states at the gate interface, the gate insulator is an epitaxial composite layer formed by an appropriate superlattice of which the portion adjacent the channel region is free of intentional doping. The superlattice may comprise, for example, alternating layers of aluminum antimonide and aluminum arsenide or of aluminum antimonide and gallium arsenide.

Abstract: An EPROM as a nonvolatile semiconductor memory device includes a semiconductor substrate 1, a gate oxide layer 3 formed on the surface of the semiconductor substrate 1, a plurality of floating gates 4a and 4b formed on the gate oxide layer 3 so as to overlap one another at the portions 4ab thereof with a gate oxide layer 14 sandwiched between the overlapping portions 4ab, and control gate strips 5 formed on a gate oxide layer 6 which overlies the floating gates 4a and 4b.

Abstract: A packaged semiconductor device includes trapezoidal power leads and an earth lead in a resin package. The power and earth leads have a large area, radiate heat, and reduce inductance, improving the electrical characteristics of the packaged semiconductor device.

Abstract: In a filed effect transistor utilizing two-dimensional electron gas as an active layer, an improvement to increase sheet electron density in a cap layer has been made by inserting into the cap layer at an interface with a carrier supplying layer, a thin film comprising a material having an electron affinity larger than that of a material constituting the cap layer. Further by employing a non-doped material for this thin film layer, electron mobility in the cap layer can also be improved. Thus source resistance of the field effect transistor has been reduced.

Abstract: In a MOS-controlled thyristor MCT, the second base layer (16) is pulled to the cathode-side surface of the semiconductor substrate (1) between the MCT until cells. At this point, a collector zone (20), which is doped oppositely to the second base layer (16) is arranged which is connected to the cathode contact (2) and reaches into the second base layer (16). Together with the second base layer (16) and an additional opposite anode short circuit, the collector zone (20) forms an inverse diode structure (11) which saves an external free-wheeling diode when inductive loads are switched.

Abstract: An insulation film is formed on a semiconductor substrate in which semiconductor elements are formed. A plurality of wiring layers and interlaid insulation films are alternately laminated on the insulation film. The design margins of the laminated wiring layers and via holes formed in the interlaid insulation films are set to be larger as they are set at a higher level. The design margin is determined by using the focus margin, mask misalignment due to the mask alignment accuracy, pattern size conversion error, warp of the semiconductor substrate and irregularity of the surface of the semiconductor substrate as parameters.

Abstract: A semiconductor device (10) has a bipolar transistor merged with an MOS transistor, the two transistors being separated essentially by a sidewall spacer and the bipolar transistor being self-aligned to the MOS transistor. The MOS transistor includes a gate (22) and a sorce region (38). A drain region of the MOS transistor is also an active base region (27) of the bipolar transistor. The bipoloar transistor further includes a first emitter region (40) formed in the active base region and a second emitter region (32) which is formed on the first emitter region and partially overlies the MOS transistor gate. The second emitter region is separated from the gate by a sidewall spacer (29) and an overlying dielectric layer (23).