Abstract: An organic light-emitting display apparatus includes: a substrate; pixels defined on the substrate, where each pixel includes a first region including a light-emitting region and a second region including a transmission region; a third region defined on the substrate disposed between the pixels; first electrodes disposed in the pixels on the substrate, respectively, where each first electrode is disposed in the first region of a corresponding pixel; an organic emission layer disposed to cover the first electrodes; a first auxiliary layer disposed on the organic emission layer in the second region and which exposes the first region; a second electrode disposed on the organic emission layer in the first region; a second auxiliary layer disposed in the first and second regions and which exposes the third region; and a third electrode disposed in the third region and in contact with the second electrode.

Abstract: A display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area is necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and whose end portions are over the first oxide semiconductor layer and overlap with the gate electrode. The gate electrode of the non-linear element is connected to a scan line or a signal line, the first wiring layer or the second wiring layer of the non-linear element is directly connected to the gate electrode layer so as to apply potential of the gate electrode.

Abstract: According to one embodiment, a semiconductor light emitting element includes a first electrode, first and second light emitting units, first and second conductive layers, a first connection electrode, a first dielectric layer, first and second pads, and a first inter-light emitting unit dielectric layer. The first light emitting unit includes first and second semiconductor layers, and a first light emitting layer. The first semiconductor layer includes a first semiconductor portion and a second semiconductor portion. The second light emitting unit includes a third semiconductor layer, a fourth semiconductor layer, and a second light emitting layer. The fourth semiconductor layer is electrically connected with the first electrode. The first conductive layer is electrically connected with the third semiconductor layer. The second conductive layer is electrically connected with the second semiconductor layer.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern.

Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

Abstract: A light-emitting device includes a drive transistor that controls a current to be supplied to a light-emitting element from a power supply line, an element continuity portion that electrically connects the drive transistor with the light-emitting element, an initializing transistor that is turned ON to diode-connect the drive transistor, and a connecting portion that electrically connects the drive transistor with the initializing transistor. The power supply line includes a first portion extending in a predetermined direction. The element continuity portion and the connecting portion are formed from the same layer as that of the power supply line and are located on one side along the width of the first portion across the drive transistor.

Abstract: A flip chip package includes a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein the copper column is disposed on one side of the capture pad about the via opening only.

Abstract: The invention relates to a miniaturized electrical component comprising an MEMS chip and an ASIC chip. The MEMS chip and the ASIC chip are disposed on top of each other; an internal mounting of MEMS chip and ASIC chip is connected to external electrical terminals of the electrical component by means of vias through the MEMS chip or the ASIC chip.

Abstract: A semiconductor device includes a dielectric layer in which zirconium, hafnium, and a IV group element are mixed. A method for fabricating a capacitor includes forming a bottom electrode, forming the dielectric layer and forming a top electrode over the dielectric layer.

Abstract: An organic light-emitting device includes a substrate; a first electrode layer and a second electrode layer on the substrate, in parallel to the substrate, and facing each other; an emission layer between the first electrode layer and the second electrode layer, where the emission layer includes a first emission region, a second emission region, and a third emission region, where the emission layer includes a first common emission layer in the first emission region, the second emission region, and the third emission region; a second emission layer in the second emission region between the first common emission layer and the second electrode layer; and a third emission layer in the third emission region between the first common emission layer and the second electrode layer, and where the first common emission layer includes a first host, a first dopant, and a p-type dopant.

Abstract: A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate contains a nanowire mesh device and a second portion of the SOI substrate contains a partially depleted semiconductor on insulator (PDSOI) device. The nanowire mesh device includes stacked and spaced apart semiconductor nanowires located on the SOI substrate with each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region. The nanowire mesh device further includes a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires. The PDSOI device includes a partially depleted semiconductor layer on the substrate, and a gate region over at least a portion of the partially depleted semiconductor layer.

Abstract: There are disclosed herein various implementations of an integrated half-bridge circuit with low side and high side composite switches. In one exemplary implementation, such an integrated half-bridge circuit includes a III-N body including first and second III-N field-effect transistors (FETs) monolithically integrated with and situated over a first group IV FET. The integrated half-bridge circuit also includes a second group IV FET stacked over the III-N body. The first group IV FET is cascoded with the first III-N FET to provide one of the low side and the high side composite switches, and the second group IV FET is cascoded with the second III-N FET to provide the other of the low side and the high side composite switches.

Abstract: The present invention provides a power transistor device with a super junction including a substrate, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The first epitaxial layer is disposed on the substrate, and has a plurality of trenches. The trenches are filled up with the second epitaxial layer, and a top surface of the second epitaxial layer is higher than a top surface of the first epitaxial layer. The second epitaxial layer has a plurality of through holes penetrating through the second epitaxial layer and disposed on the first epitaxial layer. The second epitaxial layer and the first epitaxial layer have different conductivity types. The through holes are filled up with the third epitaxial layer, and the third epitaxial layer is in contact with the first epitaxial layer. The third epitaxial layer and the first epitaxial layer have the same conductivity type.

Abstract: A semiconductor device includes a first insulating film formed above a semiconductor substrate, a fuse formed above the first insulating film, a second insulating film formed above the first insulating film and the fuse and including an opening reaching the fuse, and a third insulating film formed above the second insulating film and in the opening.

Abstract: A device includes a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region and a plurality of layer pairs disposed within one of the n-type region and the p-type region. Each layer pair includes an InGaN layer and pit-filling layer in direct contact with the InGaN layer. The pit-filling layer may fill in pits formed in the InGaN layer.

Abstract: An object of the present invention is to provide a hardening method and a hardening device capable of successfully hardening a shaft and an inner wall of a hole of a work in which the hole is formed close to the shaft on a flat plate. A hardening device for hardening a shaft and an inner wall of a hole, the shaft extending vertically from a flat plate and the hole being formed adjacent to the shaft, includes a first heating coil that is a conductive body facing the shaft and a second heating coil that is a helical conductive body having at least a portion inserted into the hole, so that the first heating coil and the second heating coil heat the shaft and the inner wall of the hole respectively and simultaneously.

Abstract: An embodiment of an electronic device includes first and second semiconductor bodies. The first semiconductor body houses a first conductive strip having a first end portion and a second end portion, and houses a first conduction terminal electrically coupled to the first end portion and facing a surface of the first semiconductor body. The second semiconductor body houses a second conductive strip having a third end portion and a fourth end portion, and houses a second conduction terminal electrically coupled to the third end portion and facing a surface of the second semiconductor body. The first and second semiconductor bodies are arranged relative to one another so that the respective surfaces face one another, and the first conduction terminal and the second conduction terminal are coupled to one another by means of a conductive element so as to form a loop of an inductor.

Abstract: A semiconductor memory device of the present invention includes a first dielectric layer located on an upper surface of a semiconductor substrate including contact area and a non-contact area, an etching stop layer pattern formed to expose the first dielectric layer in the non-contact area and cover the first dielectric layer in the contact area, a contact hole extended to the semiconductor substrate of the contact area through the etching stop layer pattern and the first dielectric layer, a contact plug located in the contact hole, and a conductive line connected to the contact plug.

Abstract: A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices.

Abstract: A semiconductor device includes a plurality of semiconductor elements each having a front surface and a back surface; a front surface-side heatsink that is positioned on a front-surface side of the semiconductor elements and dissipates heat generated by the semiconductor elements; a back surface-side heatsink that is positioned on a back surface-side of the semiconductor elements and dissipates heat generated by the semiconductor elements; a sealing material that covers the semiconductor device except for a front surface of the front surface-side heatsink and a back surface of the back surface-side heatsink; a primer that is coated on at least one of the front surface-side heatsink and the back surface-side heatsink and improves contact with the sealing member; and a protruding portion positioned between the plurality of semiconductor elements, on at least one of the back surface of the front surface-side heatsink and the front surface of the back surface-side heatsink.