Patents Examined by Edward Wojiechowicz
  • Patent number: 6515334
    Abstract: There is disclosed a hybrid circuit in which a circuit formed by TFTs is integrated with an RF filter. The TFTs are fabricated on a quartz substrate. A ceramic filter forming the RF filter is fabricated on another substrate. Terminals extend through the quartz substrate. The TFTs are connected with the ceramic filter via the terminals. Thus, an RF module is constructed.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: February 4, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto
  • Patent number: 6445039
    Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.
    Type: Grant
    Filed: January 14, 2000
    Date of Patent: September 3, 2002
    Assignee: Broadcom Corporation
    Inventors: Agnes N. Woo, Kenneth R. Kindsfater, Fang Lu
  • Patent number: 6111280
    Abstract: A gas-sensing semiconductor device 1 is fabricated on a silicon substrate 2 having a thin silicon oxide insulating layer 3 on one side and a thin silicon layer 4 on top of the insulating layer 3 using CMOS SOI technology. The silicon layer 4 may be in the form of an island surrounded by a silicon oxide insulating barrier layer 4 formed by the known LOCOS oxidation technique, although other lateral isolation techniques may also be used. The device 1 includes at least one sensing area provided with a gas-sensitive layer 18, a MOSFET heater 6 for heating the gas-sensitive layer 18 to promote gas reaction with the gas-sensitive layer 18 and a sensor 16, which may be in the form of a chemoresistor, for providing an electrical output indicative of gas reaction with the gas-sensitive layer 18. As one of the final fabrication steps, the substrate 2 is back-etched so as to form a thin membrane 20 in the sensing area. Such a device can be produced at low cost using conventional CMOS SOI technology.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: August 29, 2000
    Assignee: University of Warwick
    Inventors: Julian Gardner, Florin Udrea