Abstract: A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.

Abstract: Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.

Abstract: Methods, systems, and computer programs are presented for providing backup services to a database. One method includes operations for installing a backup agent in a first database, receiving information about the first database, and executing, by the backup agent, queries to the first database to determine a topology of the first database. Further, the method includes configuring, based on the topology, a receiver service of a second database for backing up the first database in the second database. The backup agent configures an interface module of the first database to back up the first database to the second database. The configuration includes an interface to the receiver service of the second database and connection information for storing data in one or more nodes of the second database. The interface module streams updates from the first database to the second database based on the configuration of the interface module.

Abstract: Each node of a storage cluster determines its capabilities and advertises the set of capabilities along with respective capability weights to other nodes of the storage cluster. Nodes monitor their systems for capability changes and, as capabilities of the nodes dynamically change, the dynamic changes to the node capabilities are similarly advertised. The advertised capabilities are passed to a cluster service manager which creates capabilities groups based on the advertised capabilities of the nodes. When a service is deployed to the storage cluster or moved within the cluster, the cluster service manager determines the set of required capabilities associated with the service, and uses the capabilities groups to identify nodes of the storage cluster for implementation of the service. Where more than one node has advertised the required sets of capabilities, the weights are used in an election process to determine which node should be used to implement the service.

Abstract: A zoned namespace storage device system includes a zoned namespace storage device coupled to a computing device. The zoned namespace storage device includes a zoned namespace storage subsystem that is configured to store data, and storage device compute hardware that is coupled to the zoned namespace storage subsystem and that is configured to provide a storage device operating system that includes a storage device management microservice. The storage device management microservice presents a non-zone storage service to a host subsystem in the computing device and receives, via the non-zone storage service presented to the host subsystem, a storage command from the host subsystem that is associated with a storage operation. The storage device management microservice then utilizes a zone storage service presented to the storage device management microservice by the zoned namespace storage subsystem to perform the storage operation on the zoned namespace storage subsystem.

Abstract: Apparatus transmits an identifier for association with a virtual area by an administering network service, generates output data from human perceptible stimulus in a physical space, transmits the output data in connection with the virtual area, receives input data associated with the virtual area, and generates human perceptible stimulus in the physical space from the input data. A persistent association is created between the apparatus and a virtual area. A respective presence is established in the virtual area for a communicant operating a client network node connected to the virtual area. A respective connection between each active pair of complementary sources and sinks of the client network node and the apparatus are administered in association with the virtual area. A client network node displays a graphical user interface, establishes the administered connections, and presents interaction controls associated with the object for interacting with communicants in the physical space.

Abstract: An apparatus includes an output bus configured to store data, a match table, one or more storage devices, and logic. The match table is configured to store a plurality of entries, each entry including a key value, wherein the match table specifies a matching entry in response to being queried by the query data. The one or more storage devices are configured to store operation information for each of the plurality of entries stored in the match table. The operation information specifies one or more instructions associated with each respective entry in the plurality of entries stored in the match table. The logic is configured to receive one or more operands from the output bus, identify one or more instructions from the one or more storage devices, and generate, based on the one or more instructions and the one or more operands, processed data.

Abstract: An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.

Abstract: Systems, apparatuses, and methods for implementing a unified kernel virtual address space for heterogeneous computing are disclosed. A system includes at least a first subsystem running a first kernel, an input/output memory management unit (IOMMU), and a second subsystem running a second kernel. In order to share a memory buffer between the two subsystems, the first subsystem allocates a block of memory in part of the system memory controlled by the first subsystem. A first mapping is created from a first logical address of the kernel address space of the first subsystem to the block of memory. Then, the IOMMU creates a second mapping to map the physical address of that block of memory from a second logical address of the kernel address space of the second subsystem. These mappings allow the first and second subsystems to share buffer pointers which reference the block of memory.

Abstract: Embodiments relate to coordinating the operations of subsystems in a communication system of an electronic device where a coexistence hub device monitors the state information transmitted as coexistence messages over one or more multi-drop buses, processes the monitored coexistence messages and sends out control messages as coexistence messages to other systems on chips (SOCs). The coexistence hub device can also update the operations of the communication system. The coexistence hub device may receive an operation policy from a central processor and may execute the operation policy without further coordination of the central processor. The coexistence hub device broadcasts the control messages as coexistence messages according to the executed operation policy.

Abstract: Coalescing write operations in a cloud-based storage system including receiving, from a storage controller application of the cloud-based storage system, a first plurality of write operations, wherein each of the first plurality of write operations comprises a respective write to a storage volume; coalescing the first plurality of write operations into a plurality of coalesced write operations, wherein each of the coalesced write operations are configured to effect two or more of the first plurality of write operations; and performing the plurality of coalesced write operations on the storage volume.

Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.

Abstract: A system or a device can include a processor core comprising one or more hardware processors; a processor memory to cache data; a memory link interface to couple the processor core with one or more attached memory units; and a platform firmware to determine that a device is connected to the processor core across the memory link interface; determine that the device comprises an attached memory; determine a range of at least a portion of the attached memory available for the processor core; map the range of the portion of the attached memory to the processor memory; and wherein the processor core is to use the range of the portion of the attached memory and the processor memory to cache data.

Abstract: A hydrogen sensor includes a communication terminal, a plurality of identification terminals, and an ID setting section. The communication terminal is connected to a first communication bus or a second communication bus, and communicate with a vehicle ECU. Each of the plurality of identification terminals is set to either an open state (OPEN) in which the identification terminal is not connected to any potential or a grounded state (GND) in which the identification terminal is connected to a ground potential. The ID setting section sets an identifier in either a standard format or an extended format, according to a difference in the communication bus to which the communication terminal is connected.

Abstract: A system comprises a communications module; a processor coupled to the communications module; and a memory coupled to the processor, the memory storing processor-executable instructions which, when executed by the processor, configure the processor to receive, via the communications module, a transfer instruction for transfer of data from a first data record associated with a transferor to a second data record associated with a recipient, the transfer instruction including a transfer amount and a condition associated with the transfer; send, via the communications module, a notification of the transfer instruction to a computing device associated with the recipient and request permission to obtain contextual data therefrom; when permission is granted, obtain, via the communications module, contextual data from the computing device; determine, based on the contextual data, that the condition associated with the transfer has been satisfied; and in response to determining that the condition associated with the t

Abstract: An apparatus supports single root input/output virtualization (SR-IOV) capable devices. The apparatus includes input/output ports, and SR-IOV capable PCIe devices. Each SR-IOV capable PCIe device has one or more namespaces or controller memory buffers. The SR-IOV capable PCIe device provides one or more physical functions and virtual functions that can access the one or more namespaces or controller memory buffers. A PCIe switch controller communicates with host servers coupled to the input/output ports, and assigns one or more virtual functions to each host device, and enables the host devices to access one or more namespaces or controller memory buffers through the assigned virtual functions.

Abstract: An example method of threshold voltage offset calibration at memory device power up comprises: identifying a set of memory pages that have been programmed within a time window; determining, for each voltage offset bin of a plurality of voltage offset bins, a corresponding value of a data state metric produced by a memory access operation with respect to a memory page of the set of memory pages, wherein the memory access operation utilizes a voltage offset associated with the voltage offset bin; identifying a subset of the plurality of voltage offset bins, such that memory access operations performed using the corresponding voltage offsets produced respective values of the data state metric that satisfy a predefined quality criterion; selecting, among the subset of the plurality of voltage offset bins, a voltage offset bin that is associated with the lowest voltage offset; and associating the set of memory pages with the selected voltage offset bin.

Abstract: According to one embodiment, a communication device includes: a voltage detector configured to detect a voltage from a first signal line to which the communication device and a master device are connected; and a controller configured to output, in case of detecting a read-out command from a second signal line to which the communication device and the master device are connected, a first signal with a time length corresponding to a value of the voltage to a third signal line to which the communication device and the master device are connected, and output, in case that a first signal is not detected on the third signal line from another communication device different from the master device after output of the first signal ends, a second signal including information corresponding to the read-out command to the second signal line.

Abstract: Methods and systems associated with data modification are described. Examples can include receiving, at a controller of a device, data associated with a read or write command transmitted to a memory resource and modifying the data using logic before transmitting the data to a host or image sensor or before writing the data to the memory resource. The modification can include removing one or more bits from the data, reordering one or more bits of the data, changing a format of the data, or any combination thereof. The modified data can be transmitted to the host or image sensor or written to the memory resource. In some examples, a plurality of memory devices can combine modified data for transmitting to a host.

Abstract: Methods, systems, and devices for redundant computing across planes are described. A device may perform a computational operation on first data that is stored in a first plane that includes content-addressable memory cells. The first data may be representative of a set of contiguous bits of a vector. The device may perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane. The second data may be representative of the set of contiguous bits of the vector. The device may read from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.