Abstract: A semiconductor device includes a common bus and a plurality of macros connected in series by connections. Each of the macros is constructed by an internal circuit, a buffer connected between an input of the internal circuit and the common bus, a register connected to the common bus, and a logic circuit for selecting one of an output signal of the internal circuit and an output signal of the register.

Abstract: The invention is a modem and associated method of data transmission which improve the protection afforded to data under conditions of occasional impulsive noise. The modem is ideally suited for use with another modem of similar type in a system whereby data is transmitted as a sequence of frames in either direction. Each modem applies forward error correction (FEC) to frames transmitted to the other modem. If a particular frame is corrupted on its way from a “first” modem to a “second” modem, the second modem attempts to correct these errors. If it is unable to do so, then the second modem will request a retransmission by placing a binary encoded message in the error field of a frame transmitted towards the first modem. The binary encoded message is itself protected from errors by a suitable combination of zeroes and ones. The second modem then sets a timer and subsequently ignores all frames received from the first modem until the timer expires.

Abstract: The present invention provides for storage and transmission of digital data by analog media, discrete and continuous, and more particularly to digital data representation for multi-bit data storage and transmission, using means to trade Ns (media noise) with Np (process contributed noise), thus allowing for storage of more bits per memory cell or increase capacity of transmission channel when compared to the amounts attainable by common practice. The storage media may be of any analog type, such as FLASH, RAM (D or S), EPROMS of various types and even used with continuous analog data storage or transmission.

Abstract: Disclosed is a thermal asperity pointer processing apparatus and method for processing apparatus for generating erasure locations from a thermal asperity signal. The thermal asperity signal indicates an error burst in an interleaved data sector. The apparatus includes a thermal asperity pointer recorder, a storage unit, and a thermal asperity pointer processing unit. The thermal asperity pointer recorder is adapted to receive a thermal asperity signal and is configured to generate a thermal asperity event information associated with the thermal asperity signal. The thermal asperity event information includes a thermal asperity duration, a starting interleave number, and a starting interleave address of the thermal asperity signal in the interleaved data sector.

Abstract: A circuit for monitoring and detecting data transfer protocol errors that occur during asynchronous transfer of data over a data bus. The circuit monitors bus request/acknowledge control lines in accordance with a predetermined handshaking protocol. In the event that an undefined or illegal logic state is detected on the data bus request or acknowledge control lines, the circuit provides an error value to the data sending entity. As a result of receiving this error value, the data sending entity can retry the data transmission over data bus.

Abstract: A semiconductor test system for efficiently testing a semiconductor device (DUT) having a phase lock loop (PLL) circuit therein. The semiconductor test system includes a first clock and waveform generator for supplying a clock signal to the PLL circuit at a start of the first pattern block, a second clock and waveform generator for supplying pattern data to the DUT during each of the pattern blocks, a pattern generator for generating pattern data, and a timing generator for generating a tester rate signal, a clear signal, and a gate signal for controlling the tester rate signal and the clear signal in the first and second clock and waveform generators. The clock signal is continuously provided to the PLL circuit until the end of the last pattern block while the pattern data to the data pin is reset between the end of the current pattern block and the start of the next pattern block.

Abstract: An apparatus and method for error correction in an optical disk system are described. An optical disk reproducing system calculates syndromes for each codeword to set an eraser flag during EFM demodulation. Error-correction-coding is performed using the eraser flag after completion of EFM-demodulation to reduce the access time for a data memory in error correction, thus reducing the time of error correction. The system includes a data memory for storing the EFM signals and the EFM-demodulated signals in the unit of an error correction block, an EFM demodulation and syndrome calculator for EFM-demodulating the EFM signals to output the EFM-demodulated signals to the data memory, and for calculating syndromes of the EFM-demodulated signals in the unit of the first codeword and outputting a flag indicating errors.

Abstract: As system-on-a-chip (SOC) designs become popular these days, the number of embedded cores in a chip gets larger, raising test issues of glue logic test as well as embedded core test. A core-embedded integrated circuit comprising a first logic block, a second logic block, a signal line coupled between the first logic block and the second logic block for inputting/outputting an input/output signal of the logic blocks, and a boundary scan cell coupled to the signal line for loading /capturing the input/output signal for testing one or both of the first logic block and the second logic block (individually or together), with minimum overhead. Each boundary scan cell includes a data holding capability for data loading from the first and/or second logic block, wherein each boundary scan cell is adapted for serial connection with another of a plurality of like boundary scan cells (boundary scan cell chaining).

Abstract: An event based test system for testing an electronics device under test (DUT) by supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. The event based test system includes an event memory for storing timing data of each event which represents a time difference between two adjacent events, an address sequencer for generating address data for accessing the event memory, a timing count logic for summing the timing data to produce an overall time of each event relative to a predetermined reference point, an event generation circuit for generating each event based on the overall time for formulating the test signal or strobe signals, and a host computer for controlling an overall operation of the event based test system.

Abstract: In a method of test pattern generation for logic circuits, a whole circuit is divided into a plurality of partial circuits for test pattern generation by distributed-processing. ATG (Algorithmic Test Generation) process is performed per each of the partial circuits based on the result of RTG (Random Test Generation) process. Also disclosed are a test pattern generation system performing the method, and computer readable media having program for the test pattern generation system to perform the method.

Abstract: A method for evaluating the robustness of a logic circuit to soft errors involves injecting a current pulse into a node of the logic circuit. The current pulse is shaped to be representative of a high-energy particle strike, and may have an amplitude that is sufficient to momentarily discharge an output node of the logic circuit. The output node of the logic circuit is electrically monitored to determine whether a transition occurs from a first logic state to a second logic state in response to the injected current pulse. In the case where the state of the output node does flip in response to the injected current pulse, a waveform of the injected current pulse is integrated over time to compute a critical charge level (QCRIT). Where the amplitude is insufficient to cause the output node to flip, the amplitude of the injected current pulse is incremented and the above steps are repeated using the incremented amplitude until a logic state transition does occur at the output node.

Abstract: A data block includes a plurality of sub-blocks. Each sub-block includes a sub-block check bit that may be used to detect the presence of a bit error within the sub-block. A composite sub-block is generated, which is the column-wise exclusive-or of the bits of each sub-block. In one embodiment, the composite sub-block is not stored, but rather used for computational purposes only. A plurality of composite check bits is used to detect a bit position of a bit error within the composite sub-block. If a bit error within the data block occurs, the sub-block check bits may be used to detect in which sub-block the error occurred. The composite check bits may be used to determine which bit position of the composite sub-block is erroneous. The erroneous bit position of the composite sub-block also identifies the bit position of the erroneous bit in the sub-block identified by the sub-block check bits.

Abstract: The data contents of memory systems are usually protected via an EDC system. When an error is present in the memory system, the EDC system can only recognize this error after the readout of faulty data.

Abstract: A technique to detect and correct single bit errors and to detect paired bit errors in a data block. Two bits of the data block are paired and transferred on the same data path in different cycles. Check bits are computed prior to transferring the data block. A syndrome bits vector is computed when the data block is received. The syndrome bits vector includes a number of syndrome bits that is identical to the number of check bits. A value of the syndrome bits vector is used to detect and correct single bit errors and to detect paired double bit errors that occur in the data block without using an extended check bit. If the syndrome bits vector contains all zero bits, the data block is accepted without modification. If the syndrome bits vector is identical to a predetermined special vector V, a paired double bit error has occurred and either an unrecoverable error message is generated or a re-operation on the data block is requested.

Abstract: A high speed A/D converter includes a series of encoder sections for converting a thermometer code to a gray code and an error signal production section for detecting a babble error in the gray code and generating an error signal indicating such a babble error. An error correction section corrects babble errors in the gray code in response to the error signal. The corrected gray code is then converted to a binary code with a gray code to binary code converter. When the high speed A/D converter is incorporated in a semiconductor device, the A/D converter may be tested using a sampling clock having a phase which varies successively with respect to the input analog signal to sample the analog signal, and then evaluating the corresponding generated digital signal.

Abstract: The present invention comprises a number transformer that includes at least one updatable parameter, for example a ring counter, that produces an N-nary number. The N-nary number has several bits, exactly one of which has a value of one and the remaining of which have a value of zero. The number transformer also includes a masker, configured to perform a bitwise boolean AND upon the first updatable parameter and a binary number. The binary number is obtained from a linear finite state machine operating as a pseudorandom pattern generator. When several ring counters are included, multiplexers are added to select one of the ring counters. The multiplexers are controlled by a ROM, that iterates through the various test points in a circuit under test.

Abstract: A timing adjustment circuit is used for a semiconductor test system having a plurality of test stations for testing a plurality of semiconductor devices in parallel at the same time.

Abstract: To provide a semiconductor memory device having an ECC circuit whereof checker-data inspection of memory cells in the user areas and the ECC areas can be performed at once, the ECC code generation circuit generates the ECC code of six bits whereof logic of each bit has XOR logic of each of six different combinations of 15 bits of the data set of 32 bits, and addresses in every user areas of the bit-columns are arranged in an order of 1, 4, 2, 5, 3, 6, . . . , b, f. When a checkerboard pattern is written, a first data set having 32 bits of logic ‘0’ and a second data set having 32 bits of logic ‘1’ are written alternately, in addresses 4n to 4n+3 and 4(n+1) to 4(n+1)+3 of the user areas on odd-numbered word-lines, and written alternately on even-numbered word-lines in an inverse order of the odd-numbered word-lines, when checker-data inspection of the memory-cell array is performed, n being an integer not less than 0.