Patents Examined by Emmauel Bayard
  • Patent number: 6763056
    Abstract: A path timing detecting circuit can save consumed current by omitting correlative arithmetic operations (cumulation) for unnecessarily long correlation lengths L when a propagation environment is relatively good, and a plurality of paths can be detected with high precision. The path timing detector circuit performing a correlative arithmetic operation of a spread modulation wave and a predetermined spread code with a given period of delay and detecting a reception timing of the spread modulation signal via each path on the basis of a result of the correlative arithmetic operation, includes a monitoring circuit for monitoring whether a cumulated value exceeds a threshold value during a process of the correlative arithmetic operation and a correlative arithmetic operation control circuit responsive to the cumulated value in excess of the threshold value for stopping the correlative arithmetic operation in a corresponding delay period.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: July 13, 2004
    Assignee: NEC Corporation
    Inventor: Michihiro Ohsuge