Abstract: A graphics processing system for operation with a data store, comprising: one or more processing units for processing tasks; a check unit operable to form a signature which is characteristic of an output from processing a task on a processing unit; and a fault detection unit operable to compare signatures formed at the check unit; wherein the graphics processing system is operable to process each task first and second times at the one or more processing units so as to, respectively, generate first and second processed outputs, the graphics processing system being configured to: write out the first processed output to the data store; read back the first processed output from the data store and form at the check unit a first signature which is characteristic of the first processed output as read back from the data store; form at the check unit a second signature which is characteristic of the second processed output; compare the first and second signatures at the fault detection unit; and raise a fault signal i

Abstract: A system performs verification of Ethernet hardware. A data frame including a first portion for storing a checksum value and a second portion for storing a timestamp value is received. The second portion of data frame is set to zero. A timestamp value for including in second portion of the data frame is received. A modified checksum value is determined based on the checksum value included in the first portion of the data frame and the timestamp value. A cyclic redundancy check (CRC) value is determined for the data frame by nullifying the checksum value in the data frame and considering the timestamp value. A final CRC value is determined by combining the CRC value for the data frame and a CRC correction value based on the checksum. The modified data frame is sent for processing using an emulator.

Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

Abstract: A high-dimensional non-orthogonal transmission method is provided. In the method, signals of various users are mapped to form high-dimensional signals, and the high-dimensional signals are pre-coded, such that non-orthogonal transmission is realized in a higher dimension. Moreover, different users perform matched receiving on respective signals, and non-orthogonal transmission signals can be recovered merely by means of a receiver with a linear complexity. By means of the method, multi-user data non-orthogonal transmission can be realized without depending on conditions such as user pairing and collaboration, and various users do not need to perform iterative feedback, such that the detection complexity of non-orthogonal multi-user signals is significantly reduced.

Abstract: A parity generation operation based on a set of multiple planes of host data is executed to generate a set of multi-page parity data. The set of multi-page parity data is stored in a cache memory of a memory device. A data recovery operation is performed based on the set of multi-page parity data.

Abstract: A memory device comprises a plurality of memory cells and a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device. The memory device further comprises an interconnection unit configured for connecting the plurality of memory cells to a first assignment of evaluation elements in a first state and for connecting the same plurality of memory cells to a second assignment of the evaluation elements in a second state. The memory device comprises an evaluation unit configured for controlling the interconnection unit to transition from the first state to the second state. The evaluation unit is configured for evaluating the plurality of memory cells in the first state to obtain a first evaluation result, and for evaluating the plurality of memory cells in the second state to obtain a second evaluation result.

Abstract: The present disclosure relates to a method for installing a program code packet onto a device. A processor device of the device receives the program code packet via a first data connection from a device-external data source and forms a checksum value in response to the received program code packet. A controller which differs from the processor device is operated in the device. The controller receives a reference checksum value from a specified device-external update server device via a second data connection, which differs from the first data connection, and the checksum value formed by the processor device from same, and a specified installation procedure for installing the program code packet on the processor device is initiated by the controller in the processor device only in the event that the checksum value and the reference checksum value are identical.

Abstract: The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.

Abstract: In one embodiment, a method is provided. The method includes receiving a request for a first set of data stored on a data storage system from a computing device. The method also includes retrieving the first set of data from a data storage device of the data storage system. The method further includes generating a set of codewords based on the first set of data and an error correction code. The method further includes transmitting a set of network packets to the computing device. Each network packet of the set of network packets comprises a codeword from the set of codewords.

Abstract: A network interface for a storage controller includes a processor and a memory that stores an instruction code to be executed by the processor. The processor executes protocol processing for transmitting and receiving packets via a network. The processor reproduces a first packet not received from the network, from a plurality of other received packets included in an error correction packet group same as that of the first packet.

Abstract: Methods, apparatus, systems and procedures to manage a multicast communication to a multicast group implemented by a respective wireless transmit/receive unit (WTRU) of WTRUs in the multicast group are disclosed. One representative method includes receiving, by the respective WTRU of the multicast group, a configuration, the configuration indicating a Random Access Channel (RACH) preamble to use for a negative acknowledgement (NACK) response to a multicast transmission to the respective WTRU, monitoring, by the respective WTRU, for data of the multicast transmission, determining, by the respective WTRU, whether the monitored for data was successfully received; and on condition that the monitored for data was not successfully received, sending, by the respective WTRU, the RACH preamble indicated by the received configuration.

Abstract: The present invention provides a method for detecting a flash memory module and an associated SoC. The method reads data in a flash memory module with a specific data format, and then determining a plurality of characteristic parameters of the flash memory module and a size of a page by decoding and checking the data. Therefore, the SoC does not need to design a one-time-programmable memory or strap pins, so as to reduce the manufacturing cost of the SoC.

Abstract: Certain aspects of the present disclosure provide techniques for wireless communication. The techniques include a method wireless communication by a user equipment including receiving a configuration message, wherein the configuration message in part configures the UE to communicate coordinated transmissions with a plurality of transmission reception points using a coordinated transmission mode. The method further includes, receiving one or more physical downlink shared channel transmissions from a plurality of transmission reception points in accordance with the coordinated transmission mode. The method further includes, selecting a HARQ-ACK feedback mode based in part on the coordinated transmission mode. The method further includes, transmitting HARQ-ACK feedback to at least one of the plurality of transmission reception points using the selected HARQ-ACK feedback mode.

Abstract: Techniques regarding calibrating one or more quantum decoder algorithms are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a correlation inversion decoder component that can calibrate a quantum decoder algorithm for decoding a quantum error-correcting code by estimating hyperedge probabilities of a decoding hypergraph that are consistent with a syndrome dataset.

Abstract: As system is provided for performing a method of receiving a superposition state defined by a sum of a plurality of addends, wherein each addend of the plurality of addends is a product between a corresponding coefficient of a plurality of coefficients and a corresponding state of a plurality of states encoded with block unary encoding. The system may identify at least one error state, of the plurality of states, having a string value that is not a block unary code string of a set of block unary code strings. The system may compute an updated superposition state based on the plurality of states without the error state.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

Abstract: A method includes determining a plurality of identifiers based on a data retrieval request. Integrity information is generated based on determining the plurality of identifiers. Stored integrity information corresponding to the data retrieval request is compared with the integrity information. When the stored integrity information compares unfavorably with the integrity information, corruption associated with the plurality of identifiers is determined.

Abstract: A system and method for indicating, via a heralding signal, that an amplitude damping decay event has occurred within a quantum low-density parity-check (LDPC) code is disclosed. Logical information may be encoded into a superconducting qubit using one or more transmons, wherein a first level and a second level are encoded into a code space of the qubit, and at least one intermediate level outside of the code space characterizes an amplitude damping decay channel which is then used to herald an amplitude damping decay event. Dynamical decoupling pulse sequences may be used to drive such qubit structures and bias noise towards the amplitude damping decay channel. The one or more heralding signals within a lower-level code may then be used as input to a quantum LDPC code for decoding syndrome measurements with the knowledge of occurrences of amplitude damping decay as indicated via the one or more heralding signals.

Abstract: The disclosure provides a method and a device in a User Equipment (UE) and a base station for wireless communication. A first node generates a first bit block, performs channel coding and then transmits a first radio signal. The first bit block comprising all bits in a second bit block and all bits in a third bit block is used for an input of the channel coding, and an output of the channel coding is used for generating the first radio signal. A Cyclic Redundancy Check (CRC) bit block of a fourth bit block is used for generating the third bit block. The fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the bits in the fifth bit block are of fixed values, and the fifth bit block is composed of K bits, the K being a positive integer.

Abstract: A storage system may include a memory device including a first region including a single-level cell and a second region different from the first region, and a storage controller configured to read data from the first region at a first gear level of a plurality of gear levels, determine an error level of the read data and a state of the memory device, and change the first gear level to a second gear level of the plurality of gear levels based on the determined error level of the data and the determined state of the memory device.