Abstract: A new method to form ROM devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a semiconductor substrate. MOS gates are formed overlying the substrate. Ions are implanted into the substrate to form lightly doped drains for the MOS gates. A masking layer is used to offset the lightly doped drains from selective MOS gates to thereby form constant-OFF MOS gates. Spacers are next formed on the sidewalls of the MOS gates. Finally, ions are implanted into the substrate to form source and drain regions for the MOS gates to thereby complete the ROM devices in the manufacture of said integrated circuit device. The method may be extended to form ROM devices from Flash gates in a FlashROM process.
Abstract: A single chamber method for depositing a stack including titanium and titanium nitride on a wafer surface. Titanium is deposited by plasma enhanced chemical vapor deposition and then plasma nitrided. Titanium nitride is subsequently deposited by a thermal chemical vapor deposition process. Advantageously, the temperatures of the substrate and showerhead as well as the internal chamber pressure are maintained at substantially constant values throughout deposition of the stack.
Type:
Grant
Filed:
April 21, 2000
Date of Patent:
August 14, 2001
Assignee:
Tokyo Electron Limited
Inventors:
Gerrit J. Leusink, Michael G. Ward, Michael S. Ameen, Joseph T. Hillman
Abstract: A semiconductor structure with a high-K insulative layer. An insulative layer is disposed on a silicon substrate and includes a first nitride layer and a high-K layer. A gate is disposed on the insulative layer. The insulative layer further includes sidewalls extending at least flush with corresponding sidewalls of the gate. Source and drain regions are disposed within the substrate adjacent to the insulative layer.