Abstract: A coating for a blade root/disk interface includes a layer of soft metal matrix, and a solid lubricant distributed through the soft metal matrix. Examples of materials include CuAl as the soft metal matrix and MoS2 as the solid lubricant, although others are also disclosed.

Abstract: A passive flow modulation device for a machine defining an axial direction and a radial direction, the passive flow modulation device including: a first ring with a first coefficient of thermal expansion; a second ring disposed coaxially with the first ring and positioned at least partially inward of the first ring along the radial direction, spaced from the first ring along the axial direction, or both, the first ring, the second ring, or both defining at least in part one or more passages, the second ring with a second coefficient of thermal expansion that is less than the first coefficient of thermal expansion to passively modulate a size of the one or more passages during operation.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a compressor comprising a rotor defining a radial direction and a circumferential direction, the rotor including a slot; a first blade and a second blade disposed in the slot, the first blade including a first platform and a first dovetail, the second blade including a second platform and a second dovetail; and a hollow block disposed circumferentially between the first blade and the second blade in the slot, the hollow block including: a platform interface portion to interface with the first platform and the second platform, the platform interface portion including a central opening defined by a circumferential face of the platform interface portion; and a hollow dovetail interface portion to couple the first dovetail and the second dovetail.

Abstract: A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.

Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.

Abstract: A method includes receiving a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections, dividing the plurality of latches into one or more clusters, determining a number of scan controls for each cluster, placing the determined scan controls in selected locations; and adjusting the scan connections based on the scan control location. A corresponding computer system and computer program product are also disclosed.

Abstract: A photomask lithography simulation model is created for making a semiconductor chip. Poor metrology is filtered and removed from a contour-specific metrology dataset to improve performance of the photomask. Filtering is performed by the application of a weighting scheme.

Abstract: A method and system for optimizing state assignments for a finite state machine. The method generates a random initial state assignment for each of a plurality of states of the finite state machine, determines an initial cost associated with the random initial state assignments, identifies a code swap to explore as a function of a code swap probability. Further, the method calculates a cost for the code swap when one or more criteria is satisfied, updates the code swap probability as a function of the cost of the code swap and a best cost, performs the code swap when the cost of the swap is smaller than the best cost and/or a current cost to optimize the state assignments, and outputs optimized state assignments.

Abstract: A method and system for optimizing state assignments for a finite state machine. The method generates a random initial state assignment for each of a plurality of states of the finite state machine, determines an initial cost associated with the random initial state assignments, identifies a code swap to explore as a function of a code swap probability. Further, the method calculates a cost for the code swap when one or more criteria is satisfied, updates the code swap probability as a function of the cost of the code swap and a best cost, performs the code swap when the cost of the swap is smaller than the best cost and/or a current cost to optimize the state assignments, and outputs optimized state assignments.

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for analyzing at least one feature in a layout representing an integrated circuit (IC) for an overlay effect. In some cases, approaches include a computer-implemented method including: modeling a topography of the IC by running at least one of a chemical mechanical polishing (CMP) model, a deposition model or an etch model on a data file representing the IC after formation of an uppermost layer; modeling the at least one feature in the IC for an overlay effect using the topography model of the IC; and modifying the data file representing the IC after formation of the uppermost layer in response to detecting the overlay effect in the at least one feature, the overlay effect occurring in a layer underlying the uppermost layer.

Abstract: Disclosed are methods and apparatus for providing feature classification for inspection of a photolithographic mask. A design database for fabrication of a mask includes polygons that are each defined by a set of vertices. Any of the polygons that abut each other are grouped together. Any grouped polygons are healed so as to eliminate interior edges of each set of grouped polygons to obtain a polygon corresponding to a covering region of such set of grouped polygons. Geometric constraints that specify requirements for detecting a plurality of feature classes are provided and used for detecting a plurality of feature classes in the polygons of the design database. The detected features classes are used to detect defects in the mask.

Abstract: A method of monitoring usage of a charging station includes collecting probe data from a plurality of electric vehicles. The probe data includes charging activity history. A usage value associated with a charging station is determined based on the collected probe data. The usage value associated with the charging station is provided to a requesting electric vehicle.

Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

Abstract: An example method for determining test conditions for at-speed transition delay fault tests on semiconductor devices is provided and includes analyzing scan patterns for testing a circuit of a device-under-test (DUT), identifying paths in the circuit activated by the scan patterns, determining behavior of the paths at different test corners, generating a histogram for each scan pattern representing a distribution of paths exhibiting worst-case behavior at corresponding test corners, generating an ordered set of scan pattern-test corner combinations based on the histogram, selecting a threshold for the ordered scan pattern-test corner combinations based on quality metrics, generating an ordered test set including the ordered scan pattern-test corner combinations with the selected threshold, and feeding the ordered test set to a test instrument, the test instrument testing the DUT according to the ordered test set, the tests being performed at the test corners listed above the selected threshold.

Abstract: A method includes detecting that a wireless charging-capable vehicle is in a charging position proximate a primary coil of a wireless charging system that is operable to wirelessly charge the vehicle via a secondary coil installed in the vehicle. The primary coil includes a top coil and a bottom coil that are substantially parallel to one another, the top coil and the bottom coil coupled to one another via a plurality of cross-coil junction units each including a switching element that routes electric current through at least a portion of one or more of the top coil and the bottom coil. The method further includes setting the switching elements such that current flowing through the primary coil produces an optimal angle of magnetic flux for wirelessly charging the vehicle given a position of the primary coil with respect to a position of the secondary coil, and causing electric current to flow through the primary coil according to the set switching elements to wirelessly charge the vehicle.

Abstract: The present disclosure shows a hybrid regulator topology that can be more easily integrated and that can maintain high efficiency across a wide output and input voltage range, even with a small inductor. The hybrid regulator topology can include two types of regulators: a flying switched-inductor regulator and a step-down regulator that divides the input voltage into an M/N fraction of the input voltage. The disclosed embodiments of the hybrid regulator topology can reduce the capacitive loss of the flying switched-inductor regulator by limiting the voltage swing across the switches in the flying switched-inductor regulator. The disclosed embodiments of the hybrid regulator topology can reduce the inductor resistive loss of the flying switched-inductor regulator by operating the flying switched-inductor regulator at a high switching frequency and with a small amount of current flow through the inductor.

Abstract: A battery includes at least one battery module line, a sensor means for determining a charging stage of a battery cell, and a control unit. The battery module line includes a plurality of battery modules mounted in series, each module having at least one battery cell and a coupling unit. The at least one battery cell is mounted between a first input and a second input of the coupling unit, and the coupling unit is configured (i) to switch the at least one battery cell between a first terminal of the battery module and a second terminal of the battery module, on a first control signal, and (ii) to connect the first terminal to the second terminal on a second control signal. The sensor means is connectable to the at least one battery cell of each battery module.

Abstract: Statistically modeling timing in a digital circuit through the use of canonical form models, where some terms of the form represent sources of variation sensitive to only a subset of timing regions of the circuit. When propagating the form through regions through which some set of terms in the model is not sensitive, those terms are collapsed by placing them in a cache and replacing them in the form with a single combined term that references the cached terms.

Abstract: An electronic arrangement for facilitating circuit layout design in connection with three-dimensional (3D) target designs, the arrangement including at least one communication interface for transferring data, at least one processor for processing instructions and other data, and a memory for storing the instructions and other data. The at least one processor being configured, in accordance with the stored instructions, to cause: obtaining and storing information in a data repository hosted by the memory, receiving design input characterizing 3D target design to be produced from a substrate, determining a mapping between locations of the 3D target design and the substrate, and establishing and providing digital output comprising human and/or machine readable instructions indicative of the mapping to a receiving entity, such as a manufacturing equipment, e.g. printing, electronics assembly and/or forming equipment.

Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.