Abstract: A storage device set includes a storage device configured to communicate with a host, the storage device including a controller configured to generate encrypted input data by encrypting data; and a reconfigurable logic chip configured to receive the encrypted input data from the storage device, generate processed data by processing the encrypted input data according to a configuration, and generate encrypted output data by encrypting the processed data.

Abstract: The present disclosure relates generally to electronic interconnects including one or more switches and, more particularly, to delay bound determination for electronic interconnects.

Abstract: Provided are a connection management mechanism and a connection management method with which computer bus connections can be managed such that failures and freezes do not occur in a computer system when delays and packet losses occur. A connection management unit, which is used in computer bus communication in which packets are transmitted between a request source and a request destination, has a dummy return packet generation/transmission function wherein a dummy return packet is generated and is transmitted to the request source when a delay or loss occurs in a return packet transmitted from the request destination, and/or a filter function wherein, after transmission of the dummy return packet, a legitimate return packet arriving from the request destination is discarded.

Abstract: The various embodiments disclose an electronic device including: a storage including a non-volatile memory having a buffer space and a storage space, a storage device controller, and a storage interface, and a processor. According to various embodiments, the processor may be configured to perform control to determine whether the storage supports a high speed data storage mode using a buffer space of a non-volatile memory of the storage, activate a function of writing data buffered in the buffer space of the non-volatile memory into a storage space of the non-volatile memory based on the storage interface operating in a first state based on the storage supporting the high speed data storage mode, and transition the storage interface of the storage to the first state based on no request to the storage being generated during a predetermined time period based on the storage interface operating in a second state.

Abstract: A data storage device and a storage system including the same are disclosed. The data storage device includes a nonvolatile memory device configured to store user data and metadata including data type identification information matched with the user data, and a controller to control the nonvolatile memory device to be switched to a cold data storage device for storing cold data only when a number of program-erase (PE) cycles of the nonvolatile memory device is equal to or larger than a reference value.

Abstract: A method of operating a Solid State Drive (SSD), comprising identifying critical metadata corresponding to data previously written to the SSD. In response to a power loss event the method also includes storing the critical metadata in a non-volatile memory. Further, the method also involves writing a first table of contents corresponding to the stored critical metadata to the non-volatile memory and storing a pointer to the first table of contents. A Solid State Drive (SSD) including a memory controller, a non-volatile memory, and a power loss protection capacitor. The memory controller is configured to identify critical metadata corresponding to data previously written to the SSD. The memory controller is also configured to, in response to a power loss event, store the critical metadata in a non-volatile memory write a first table of contents corresponding to the stored critical metadata to the non-volatile memory, and store a pointer to the first table of contents.

Abstract: A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

Abstract: A data processing system includes a plurality of resources suitable for processing data, a host suitable for requesting at least one of the plurality of resources to process the data, a plurality of data paths suitable for transferring the data between the host and the plurality of resources, and an arbiter suitable for dividing the plurality of resources into a plurality of groups, allocating at least one first data path of the plurality of data paths to each of the groups, and rearranging the plurality of groups, based on their respective transmission statuses, by additionally allocating at least one second data path of the plurality of data paths to each of the groups or by moving at least one resource from one of the plurality of groups to another of the plurality of groups.

Abstract: A server system is provided that includes one or more compute nodes that include at least one processor and a host memory device. The server system further includes a plurality of solid-state drive (SSD) devices, a local non-volatile memory express virtualization (LNV) device, and a non-transparent (NT) switch for a peripheral component interconnect express (PCIe) bus that interconnects the plurality of SSD devices and the LNV device to the at least one processor of each compute node. The LNV device is configured to virtualize hardware resources of the plurality of SSD devices. The plurality of SSD devices are configured to directly access data buffers of the host memory device. The NT switch is configured to hide the plurality of SSD devices such that the plurality of SSD devices are not visible to the at least one processor of each compute node.

Abstract: Various embodiments described herein provide for using a prefetch buffer for a data interface bridge, which can be used with a memory sub-system to increase read access or sequential read access of data from a memory device coupled to the data interface bridge.

Abstract: The controller that controls the industrial machine comprises a storage area that stores an operation program, a cache memory, a cache control unit, and an analysis unit, the analysis unit pre-reads a command subsequent to a command included in the operation program loaded in the cache memory, in a case where it is determined that an operation load on a CPU in a command included in the operation program is below a prescribed value, adds, to the command, a cache control command for loading of a subprogram into the cache memory in accordance with a predetermined condition, in a case where a subprogram call command is confirmed present, and makes a cache control request to the cache control unit, responsive to the added cache control command, and the cache control unit loads the subprogram in the cache memory, based on the cache control request.

Abstract: One or more aspects of the present disclosure relate to providing storage system configuration recommendations. System configurations of one or more storage devices can be determined based on their respective collected telemetry information. Performance of storage devices having different system configurations can be predicted based on one or more of: the collected telemetry information and each of the different system configurations. In response to receiving one or more requested performance characteristics and workload conditions, one or more recommended storage device configurations can be provided for each request based on the predicted performance characteristics, the requested performance characteristics, and the workload conditions.

Abstract: A method for protecting a system from a malicious USB device. The method includes one or more computer processors interrupting a universal serial bus (USB) enumeration process corresponding to a first USB device operatively couple to a system. The method further includes determining whether the first USB device is a human interface device (HID) based on a set of descriptor values corresponding to the first USB device. The method further includes responding to determining that that first USB device is a HID by generating a validation challenge. The method further includes presenting the validation challenge to a user of the system. The method further includes responding to determining that the user fulfils one or more actions of the validation challenge by resuming the USB enumeration process corresponding to the first USB device.

Abstract: Systems and methods for providing one-touch migration of virtual assets are described. In some embodiments, an Information Handling System (IHS), may include a processor, a remote access controller (RAC) coupled to the processor, and a memory coupled to the RAC, the RAC configured to: assume a role of an originating group's manager, where the originating group comprises a first plurality of IHSs and each IHS has one or more virtual assets of a first type; collect configuration information related to other IHSs; transmit the configuration information to another RAC of another IHS designated as a destination group's manager, comprising a second plurality of IHSs, where the other RAC is configured to: perform a compatibility check using the configuration information; and validate a migration of the one or more virtual assets from the first plurality of IHSs to the second plurality of IHSs, where migrated assets are of a second type.

Abstract: This disclosure discloses an address translation method, apparatus, and system. The method includes: receiving, by a first address translation unit (ATU), an access request sent by a first virtual machine (VM), where the access request carries a first address and parameter information of the first address, and the parameter information of the first address includes an identifier of a target virtual function (VF); determining, by the first ATU, a matching relationship based on the parameter information of the first address and VF range description information in an address mapping table; and when an identifier of a target VF and the VF range description information are successfully matched, translating, by the first ATU, the first address into a second address based on the address mapping table.

Abstract: A scalable RAID storage controller device system includes a host system coupled to a switch device by first and second NTB subsystems, first and second RAID storage devices connected to the switch device and provided in respective data storage device chassis having a storage device form factor, and first and second RAID storage controller devices connected to the switch device and provided in respective storage controller device chassis having the storage device form factor. The first RAID storage controller device executes commands received via the first NTB subsystem from the host system for a first RAID data storage system that it provides with the first RAID data storage system, and the second RAID storage controller device executes commands received via the second NTB subsystem from the host system for a second RAID data storage system that it provides with the second RAID data storage system.

Abstract: Systems and methods for memory management for virtual machines. An example method may include generating, by a Peripheral Component Interconnect (PCI) device comprising an input/output memory management unit (IOMMU), a first bit sequence and generating a second sequence by applying a predetermined transformation to the first bit sequence. The method may then write the second bit sequence to a memory buffer, read a first value from the memory buffer, write the first bit sequence to the memory buffer, and read a second value from the memory buffer. Responsive to determining that the second value does not match the first value, the method may associate a writable attribute with an IOMMU page table entry associated with the memory buffer.

Abstract: A semiconductor device includes a first master and a second master configured to issue requests for accessing to a memory, a first request issuing controller coupled to the first master, and configured to hold the request issued from the first master, a second request issuing controller coupled to the second master, and configured to hold the request issued from the second master, a bus arbiter coupled to the first request issuing controller and the second request issuing controller, a memory controller coupled to the bus arbiter, and including a buffer configured to store the requests issued from the first master and the second master, and a central bus controller configured to grant access rights to the first request issuing controller and the second request issuing controller based on space information of the buffer.

Abstract: Transferring data for a virtual machine from a source storage device to a destination storage device includes determining if either the source storage device or the destination storage device is capable of unilaterally transferring data to a storage device having only input and output capabilities. The source storage device pushes data to the destination storage device if the source storage device is capable of unilaterally transferring data to a storage device having only input and output capabilities. The destination storage device pulls data from the source storage device if the destination storage device is capable of unilaterally transferring data to a storage device having only input and output capabilities. A host computing device transfers data from the source storage device to the destination storage device in response to neither storage device being capable of unilaterally transferring data to a storage device having only input and output capabilities.

Abstract: Aspects of a storage device are provided which allow a read command to be identified for execution from multiple read commands received from a host. The storage device includes a memory configured to store a plurality of data units each comprising one or more data fragments, and metadata associated with the data units. A controller is configured to receive from the host a plurality of read commands each requesting one of the data units. The controller is further configured to identify one of the read commands based on the metadata, and to transfer the data unit associated with the identified read command to the host before transferring the data unit associated with the other read commands.