Abstract: The present invention provides a system that selectively allows an arbitration cycle to occur only when specific data is ready for transfer. That is, a flag register is provided and its output is ANDed with a bus request signal from a bus device. An arbiter will accept a bus request and initiate an arbitration cycle only when the state of a bit in the flag register indicates that actual completion data exists for the requesting device.

Abstract: A powerdown controller receives a powerdown signal and causes a powerdown if the powerdown signal indicates a powerdown condition. An override signal also forces the powerdown controller to cause the powerdown when the powerdown signal is not indicating the powerdown condition. An override circuit generates the override signal if the powerdown condition is desired and the powerdown signal is not indicating the powerdown condition.

Abstract: An apparatus and method for enabling a Peripheral Component Interconnect ("PCI") bus to support direct memory access ("DMA") transfers. The apparatus comprises a plurality of DMA controllers, a state machine and an internal storage element. The plurality of DMA controllers transfers DMA requests for an electronic device to the state machine and DMA acknowledges from the state machine to the electronic device. The state machine controls the DMA transfer by performing two transactions for each DMA transfer; namely, a memory cycle and an input/output cycle. The internal storage element acts as a buffer for this multiple cycle DMA transfer.

Abstract: A system including a plurality of electronic devices connected together through a bus, which can realize reduction in power consumption while ensuring communications. When a bias voltage on an external bus is detected by a bias detecting circuit and a comparator, a bias voltage is output from a bias output terminal to the external bus enabling it. When a driver and receiver receive a PHY-SLEEP command through the external bus, the bias voltage put from the bias output terminal to the external bus is turned off disabling it.

Abstract: A one-chip control unit for data transmission has a central processing unit for carrying out various processes according to a preliminarily stored program, a memory device for temporarily storing data processed by the central processing unit and data received from an external memory device, an input/output interface for connecting to the external memory device, bus lines connected to these components for transmitting signals therethrough, and a switch circuit for causing signals to pass through the bus lines along different routes, depending on address signals outputted from the central processing unit. The switch circuit may serve to connect the memory device with the input/output interface and to thereby enable signals to be continuously transmitted therebetween directly when the address signal outputted from the central processing unit are specifying an area on the memory device.

Abstract: A system and method for emulating the state of a soft reset within a processor device without requiring a dedicated soft reset external pin associated with said processor device. The novel system includes control circuitry coupled to a processor device for detecting a number of conditions used to cause the processor device to execute a soft reset. In processor devices that contain a write-back cache, the soft reset signal resets the configuration of the processor device and returns the processor to "real-address mode" addressing, but does not destroy the contents of the write-back cache (unlike a regular reset). Upon detecting a soft reset attempt, the novel system generates a System Management Interrupt (SMI) which is responded to by an interrupt handling routine also of the novel system. This interrupt handling routine contains a set of configuration data (stored in memory) that represents the expected state of the processor device after a soft reset.

Abstract: A method and apparatus for a method for measuring performance of an I/O bus. The method includes the steps of (a) determining a number of I/O bus clock cycles that occur during I/O bus transactions involving a peripheral device during a time period, and (b) determining a bus performance value for the I/O bus based on the number of I/O bus clock cycles determined in step (a). One embodiment of the apparatus includes a mechanism for determining a bus utilization value for the I/O bus based on the number of I/O bus clock cycles counted by the counter. Another embodiment of the apparatus includes a mechanism for determining a bus efficiency value for the I/O bus based on the number of I/O bus clock cycles counted by the counter.

Abstract: The present invention accomplishes bus utilization optimization by enabling each device to signal another bus device when it has completion information in its output buffers. For example, when an I/O device attempts to read data from a system device, a RETRY may be signalled to the requesting I/O device. A control signal is sent from the bridge to the requesting I/O device when there is completion data in its output buffers. In this manner, the present invention eliminates or reduces the multiple RETRY actions by the I/O device, since it will not attempt to obtain the data until it receives the control signal from the bridge.

Abstract: A processor device and method for booting a programmable apparatus having a signal bus having a selectable bus width. The processor device includes a microprocessor, a configurable bus interface for coupling the microprocessor to the signal bus, and a first memory. The first memory includes a bus sizing code for instructing the microprocessor for reading initial data from a pre-determined address of a second memory and configuring the bus interface to the bus width that has been selected. The first memory further includes a checksum code for a self-test of the memory, an emulator detect code for skipping the checksum code when control of the microprocessor is transferred to an emulator, a delay code for delaying a start of operation of the programmable apparatus when circuits in the programmable apparatus have a restrictive voltage requirement, and a monitor request code for transferring control to a monitor code when requested by an external user or when a self-test fails.

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer.

Abstract: A method and an apparatus for hardware and software interaction in data transfers of shared data structures in memory. The method and apparatus decreases the number of mutex lockings required to prevent conflict between different software attempting to access the same data and keeps the index value for each buffer in use in order to prevent conflicts between buffer replacement and packet arrival. In an exemplary implementation of the method and apparatus of the present invention, a receive hardware of a computer system keeps an index value for each buffer in use. This index value is placed in a completion ring protected by a mutex, and placed in a software queue protected by mutex. The mutexes assure that only one thread will possess a given index at a given time. No mutex locking is required for a buffer table containing software address and related information.