Abstract: A test pattern generation device for producing test pattern signals for testing a preselected digital circuit includes a dominant pattern signal generator and a subservient pattern signal generator. When a first dominant pattern signal (0,0,0,0,0) is generated, five subservient pattern signals (1,0,0,0,0), (0,1,0,0,0), (0,0,1,0,0), (0,0,0,1,0) and (0,0,0,0,1) are generated, each being unit Hamming distance from the dominant pattern signal. The subservient pattern signals are sequentially applied to a simulator carrying a hypothetical digital circuit for producing a controllability cost CCO.sub.f and a continuous cyclic logic value CV.sub.f at a preselected line G.sub.f in the digital circuit for each subservient pattern signal. A cost generator produces an evaluation cost CT.sub.f by the use of the controllability cost CCO.sub.f and the continuous cyclic logic value CV.sub.f for each subservient pattern signal.