Abstract: Provided is a novel chalcogen-containing organic semiconductor compound having excellent carrier mobility. The compound is represented by Formula (1a) or (1b): [Chem. 1] where in Formulas (1a) and (1b), X represents S, O, or Se, and R1 each independently represents a hydrogen atom, a halogen atom, an alkyl group, an aryl group, an aralkyl group, a pyridyl group, a furyl group, a thienyl group, or a thiazolyl group.

Abstract: Methods for selectively depositing on metallic surfaces are disclosed. Some embodiments of the disclosure utilize a hydrocarbon having at least two functional groups selected from alkene, alkyne, ketone, alcohol, ester, or combinations thereof to form a self-assembled monolayer (SAM) on metallic surfaces.

Abstract: A display apparatus including a display module having flexibility, a glass window disposed on the display module, a protective film including an adhesive layer detachably attached on the glass window, and a protecting layer disposed on the adhesive layer, a cover covering an edge of the glass window and configured to receive the display module, and a protective pattern including an edge adhesive layer attached on an edge of an upper surface of the glass window, and an edge protective layer disposed on the edge adhesive layer, in which an adhesion between the glass window and the edge adhesive layer of the protective pattern is greater than an adhesion between the glass window and the adhesive layer of the protective film.

Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.

Abstract: A pH sensor comprises: a chamber for receiving an electrolyte solution; a first and a second ion-sensitive field effect transistor (ISFETs), each of the first and second ISFETs having a source terminal, a drain terminal and a transistor channel extending between the source terminal and the drain terminal, a dielectric layer with a sensing surface arranged in the chamber so as to be contactable by the electrolyte solution, the dielectric layer separating the sensing surface from the transistor channel; a first measurement circuit configured to measure a first source-drain resistance across the transistor channel of the first ISFET; and a second measurement circuit configured to measure a second source-drain resistance across the transistor channel of the second ISFET. The first and second measurement circuits include a common reference electrode, the reference electrode arranged contactable by the electrolyte solution in the chamber.

Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.

Abstract: The gas sensor according to an exemplary embodiment of the present invention comprises: an FET device including one or more gate electrodes; a sensor array part including a plurality of sensors, in which a first electrode of each sensor is connected to at least one gate electrode of the plurality of gate electrodes in the FET device; and a controller detecting a gas using a current between a drain-source in response to voltage changes in the gate electrode of the FET device, wherein each sensor includes: a first electrode connected to a gate electrode of the FET device; a second electrode receiving an operating voltage through a switch controlled by the controller; and a detection film interposed between the first electrode and the second electrode.

Abstract: Methods for inducing reversible or permanent conductivity in wide band gap metal oxides such as Ga2O3, using light without doping, as well as related compositions and devices, are described.

Abstract: An imaging device includes a pixel electrode, a counter electrode that faces the pixel electrode, a first photoelectric conversion layer that is located between the pixel electrode and the counter electrode and that generates first signal charge, a second photoelectric conversion layer that is located between the first photoelectric conversion layer and the pixel electrode and that generates second signal charge, a first barrier layer that is located between the first photoelectric conversion layer and the second photoelectric conversion layer and that forms a first heterojunction barrier against the first signal charge in the first photoelectric conversion layer, and a charge accumulator that is electrically connected to the pixel electrode and that accumulates the first signal charge and the second signal charge.

Abstract: Devices and methods of using the devices are disclosed which can provide scalability, improved sensitivity and reduced noise for sequencing polynucleotide. Examples of the devices include a biological or solid-state nanopore, a field effect transistor (FET) sensor with improved gate controllability over the channel, and a porous structure.

Abstract: The present invention reduces an electromagnetic coupling that can occur between a first signal line provided on a first substrate and a second signal line provided on a main surface of a second substrate on the first substrate side. A wireless module (10) includes an RFIC (28), a baseband IC (16), a first substrate (11) on which first signal lines (121 through 126) for transmitting a baseband signal are provided, and a second substrate (21) provided with second signal lines (2201 through 2232) for transmitting an RF signal on a main surface (211). The first substrate (11) is provided with a pseudo conductor wall (post wall 13) for shielding the first signal lines (121 through 126) and the second signal lines (2201 through 2232).

Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.

Abstract: A curable silicone composition is disclosed. The curable silicone composition comprises: (A) a linear organopolysiloxane having at least two alkenyl groups and at least one aryl group in a molecule; (B) a branched organopolysiloxane represented by the average unit formula; (C) an organosiloxane having at least two silicon atom-bonded hydrogen atoms in a molecule; and (D) a hydrosilylation reaction catalyst. The curable silicone composition forms a cured product having good mechanical properties and good retention of transparency under conditions of high temperature.

Abstract: An approach providing a semiconductor wiring structure with a self-aligned top via on a first metal line and under a second metal line. The semiconductor wiring structure includes a plurality of first metal lines in a bottom portion of a first dielectric material. The semiconductor wiring structure includes a top via in a top portion of the first dielectric material, where the top via is over a first metal line of the plurality of first metal lines. The semiconductor wiring structure includes a second dielectric material above each of the plurality of first metal lines except the first metal line of the plurality of first metal lines. Furthermore, the semiconductor wiring structure includes a second metal line above the top via, wherein the second metal line is in a third dielectric material and a hardmask layer that is under the third dielectric material.

Abstract: A semiconductor structure manufacturing method according to the embodiments of the present application includes the following steps of: providing a semiconductor substrate; forming a first reaction layer on the semiconductor substrate; forming a second reaction layer on the first reaction layer; and thermally reacting at least a portion of the first reaction layer with at least a portion of the second reaction layer, to form an amorphous diffusion barrier layer. This amorphous diffusion barrier layer is an amorphous body with no grain boundary therein. As a result, the diffusion path for metal atoms is cut off, thereby improving the barrier effect of the barrier layer efficiently and solving the circuit performance issue caused by metal atom diffusion.

Abstract: An IC includes a source region and a drain region in a semiconductor layer. A channel region is between the source region and the drain region. A sensing well is on a back surface of the semiconductor layer and over the channel region. An interconnect structure is on a front surface of the semiconductor layer opposite the back surface of the semiconductor layer. A biosensing film lines the sensing well and contacts a bottom surface of the sensing well that is defined by the semiconductor layer. A coating of selective binding agent is over the biosensing film and configured to bind with a cardiac cell.

Abstract: An IC includes a source region and a drain region in a semiconductor layer. A channel region is between the source region and the drain region. A sensing well is on a back surface of the semiconductor layer and over the channel region. An interconnect structure is on a front surface of the semiconductor layer opposite the back surface of the semiconductor layer. A biosensing film lines the sensing well and contacts a bottom surface of the sensing well that is defined by the semiconductor layer. A coating of selective binding agent is over the biosensing film and configured to bind with a cardiac cell.

Abstract: A method for manufacturing a semiconductor memory includes: providing a portion to be processed, and performing a preset process step on the portion to be processed at least after a minimum waiting time; before performing the preset process step, performing a thermal oxidation process on the portion to be processed; and before performing the preset process step, performing a cleaning process, the cleaning process being used to remove oxides from the surface of the portion to be processed, the oxides being wholly or partly generated by the thermal oxidation process.

Abstract: A system and method for forming pixels in an image sensor is provided. In an embodiment, a semiconductor device includes an image sensor including a first pixel region and a second pixel region in a substrate, the first pixel region being adjacent to the second pixel region. A first anti-reflection coating is over the first pixel region, the first anti-reflection coating reducing reflection for a first wavelength range of incident light. A second anti-reflection coating is over the second pixel region, the second anti-reflection coating reducing reflection for a second wavelength range of incident light that is different from the first wavelength range.

Abstract: Embodiments of the present application relate to a method for manufacturing a semiconductor structure, includes: forming a contact metal layer on a silicon substrate; performing a plasma treatment process, and forming an oxygen isolation layer on a surface of the contact metal layer; and performing a silicidation reaction process, and converting the contact metal layer into a metal silicide layer.