Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

Abstract: An apparatus and method for error correction based on soft decision bits and multiple hypotheses includes: maintaining a plurality of previous single bit-flip hypotheses, each hypothesis including a respective bit-flip, a respective pre-flip bit confidence, and a respective hash responsive to the respective bit-flip; receiving a bit and a corresponding bit confidence; comparing the received bit confidence with a highest pre-flip bit confidence of the maintained plurality of single bit-flip hypotheses; and if the received bit confidence is less than the highest pre-flip bit confidence, forming a new single bit-flip hypothesis and replacing a prior bit-flip hypothesis having the highest pre-flip bit confidence with the new hypothesis.

Abstract: Apparatuses and methods are disclosed for a communication device associated with a wireless transmission. In one embodiment, a method includes performing one of a low-density parity check, LDPC, decoding process and an LDPC encoding process by loading a set of bits, in parallel, into a plurality of registers, the set of bits being distributed among the plurality of registers; one of de-interleaving and interleaving the loaded set of bits within the plurality of registers by rearranging the loaded set of bits into one of a de-interleaved and an interleaved set of bits; and after the set of bits is rearranged into the one of the de-interleaved and the interleaved set of bits within the plurality of registers, writing the one of the de-interleaved and the interleaved set of bits, in parallel, from the plurality of registers to memory.

Abstract: A memory includes a link training circuit with a pseudo-random bit sequence (PRBS) generator and a burst error detection counter. The burst error detection counter including a comparator, a first input coupled to the data input, a second input coupled to the PRBS generator, and a counter operable to increase an error count value by one responsive to detecting any number of errors greater than zero in a sequence of symbols including a predetermined number of symbols.

Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

Abstract: There is disclosed a method of operating a user equipment in a radio access network. The method includes transmitting feedback signaling utilizing a feedback resource range, the feedback resource range being determined based on a received feedback size indication and a received scheduling assignment indication. The feedback resource range being a part of a signaling resource range configured to the user equipment for transmission.

Abstract: A method for operating a storage controller includes receiving a first read command, performing a first read of data stored in a nonvolatile memory using a first read level and receiving a first read data, performing first error correction decoding of the first read data to determine whether the first error correction decoding succeeds, determining a second read level using a predetermined method, and determining a first soft decision offset value of the second read level, reading data stored in the nonvolatile memory using the determined second read level and the first soft decision offset value and receiving a first soft decision data, performing second error correction decoding of the first soft decision data to determine whether the second error correction decoding succeeds, and storing the second read level, a first method used to determine the second read level and the first soft decision offset value.

Abstract: A semiconductor memory device includes a resistive change memory device including a control circuit block and a plurality of memory decks electrically connected with the control circuit block. The semiconductor memory device includes a pattern generation block, a position correction block and a position decision block. The pattern generation block receives a row address, a column address and a deck selection signal to generate a plurality of pattern generation signals to select a plurality of memory cells in the memory deck in various patterns. The position correction block receives a temporary code for classifying the memory cells into a temporary near cell region and a temporary far cell region and for reflecting a position of the memory deck in the temporary code to output a correction code.

Abstract: Methods and encoders for encoding information bits to generate codewords for transmission across a communication channel are described. The method includes receiving input data comprising bits of information bits and frozen bits. Each bit has a value. Further, the method identifies at least one special arrangement in a subset of input data depending on locations of the information bits and the frozen bits. This subset of input data is of length L. The subset of input data has at least one special arrangement that enables direct computations instead of a series of computations to determine a preliminary output. The method generates a codeword for the input data from the preliminary output.

Abstract: Methods and apparatus for constructing polar codes are provided. A transmitter determines at least one set of parameters corresponding to data to be transmitted, and a set of sorting indices corresponding to bits of the data to be transmitted based on the set of parameters, the set of sorting indices indicating a position set of the bits to be transmitted. The transmitter polar encodes the data based at least on the set of parameters and the set of sorting indices to generate a coded block of the data, and transmits the coded block of the data.

Abstract: Methods, systems, and devices for wireless communications are described. The user equipment (UE) may initiate a successive cancellation list (SCL) decoding procedure, and may perform the SCL decoding procedure across various nodes (e.g., for each information bit through a decoding tree). At each node, the UE may determine whether a relationship between a first path metric and a second path metric satisfy a threshold. In some examples, the UE may determine whether multiple thresholds are satisfied. If conditions are satisfied (e.g., the relationship between the two path metrics satisfies a threshold), then the UE may decrease a list size of the SCL decoding.

Abstract: A method for performing low density parity check (LDPC) coding of a transmitter in a wireless communication system, according to the present disclosure, may comprise the steps of: acquiring a proto-matrix corresponding to a protograph; on the basis of weights and lifting factors of columns of the proto-matrix, acquiring one or more permuted vectors corresponding to each of the columns, a first permuted vector included in the one or more permuted vectors having been randomly generated; distributing the one or more permuted vectors for each row of a corresponding column; on the basis of the distributed one or more permuted vectors, acquiring a plurality of lifted sub matrices corresponding to a plurality of elements of the proto-matrix; generating a base graph on the basis of the plurality of lifted sub matrices; generating a parity check matrix (PCM) on the basis of the base graph; and performing LDPC coding by using the PCM.

Abstract: A computer-implemented technique for correcting a data packet having a payload and cyclic redundancy check information provides a list of possible packet errors by algorithmic operations of forcing and cancelling bits at certain positions using a generator polynomial, while maintaining the equivalence relationship with the original syndrome, performed explicitly using arithmetic operations or implicitly using a table representative of such arithmetic operations. Correction can then be implemented using an error chosen from the list.

Abstract: A method for supporting a rate-compatible non-binary LDPC code, performed by a wireless device, according to the present embodiment, comprises the steps of: acquiring a kernel part comprising a plurality of first check nodes and a plurality of first variable nodes, the kernel part having a predetermined first code rate applied thereto, and the level of each of the plurality of first variable nodes included in the kernel part being set to 2; and generating, on the basis of the kernel part, a protograph having a second code rate, when a change from the first code rate to the second code rate is required.

Abstract: Methods are proposed herein to perform rate matching for polar codes via circular buffering of the polar encoded bits. Embodiments are directed to methods of operation of a transmitting node in a wireless system including performing polar encoding of a set of information bits in accordance with a polar sequence of length NB to thereby generate NB coded bits. The method can further include interleaving the coded bits to thereby provide an interleaved coded bit sequence, and storing the interleaved coded bit sequence into a circular buffer of length NB. According to certain embodiments, the method can further include extracting N coded bits for transmission from the circular buffer. N can be greater than, equal to, or less than NB.

Abstract: A communication device includes interleaver circuitry that receives, from a host device, a first encoded data stream comprised of a plurality of symbols encoded with a first type of error correction code and interleaves the plurality of symbols of the first encoded data stream into symbol sections each including a predetermined number of symbols encoded with the first type of error correction code. Encoder circuitry encodes the first encoded data stream in accordance with a second type of error correction code different from the first type of error correction code by generating, for each of the symbol sections, an error code block corresponding to the symbols in the symbol section and outputs a second encoded data stream including the first encoded data stream and the error code block.

Abstract: A method includes encoding a sector of data to be written to a data storage device with a single error correcting code (ECC). The sector of data is divided into N individually readable and writeable portions, with N?2. The individually readable and writeable portions of the sector of data are separated with a space between the portions of the sector of data in a pattern.

Abstract: This application discloses example decoding methods, example decoders, and example decoding apparatuses. One example decoding method includes performing soft decision decoding on a first sub-codeword in a plurality of sub-codewords to obtain a hard decision result. It is determined whether to skip a decoding iteration. In response to determining not to skip the decoding iteration, a first turn-off identifier corresponding to the first sub-codeword is set to a first value based on the hard decision result. The first turn-off identifier indicates whether to perform soft decision decoding on the first sub-codeword in a next decoding iteration. The soft decision decoding is not performed on the first sub-codeword in the next decoding iteration when a value indicated by the first turn-off identifier is the first value. The hard decision result is stored.

Abstract: A decoder that is a decoding apparatus includes an error-correction decoder that executes error correction decoding processing of iteratively performing decoding processing with a window size and the number of decoding iterations indicated by decoding parameters, on received data converted into a spatially coupled low-density parity-check code, and a decoding parameter control unit that updates the decoding parameters on the basis of a decoding result obtained by the iteratively executed decoding processing.

Abstract: A Reed-Solomon decoder circuit includes: a syndrome calculator circuit to compute syndrome values for a first codeword and a second codeword sequentially supplied to the syndrome calculator circuit, where last symbols of the first codeword overlap with first symbols of the second codeword during an overlap clock cycle between: a first plurality of non-overlap clock cycles during which the first codeword is supplied to the syndrome calculator circuit; and a second plurality of non-overlap clock cycles during which the second codeword is supplied to the syndrome calculator circuit; an error locator and error evaluator polynomial calculator circuit; an error location and error value calculator circuit; an error counter; and an error corrector circuit to correct the errors in the first codeword and the second codeword based on error counts and the error magnitudes computed by an error evaluator circuit.