Abstract: A method for receiving a signal by integer forcing in a wireless communication system is provided. The method includes receiving one or more signals through a plurality of antennas, filtering the received one or more signals using a forcing matrix, generating codewords by remapping the filtered one or more signals, acquiring a summed codeword by performing a modulo operation on the codewords, decoding the summed codeword, and acquiring original codewords by performing an inversion operation on the decoded summed codeword.

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

Abstract: A semiconductor integrated circuit includes a clock recovery circuit that receive a multi-level pulse-amplitude modulated signal and to recover a clock signal. The clock recovery circuit includes a generation circuit and an oscillator. The generation circuit includes a plurality of comparators and pulse generators and a pulse summing circuit. The plurality of comparators and pulse generators compare the multi-level pulse-amplitude modulated signal with a plurality of threshold values to generate a plurality of pulses according to a plurality of comparison results. The pulse summing circuit generates a synthetic pulse based on the generated plurality of pulses. The oscillator oscillates in synchronization with the synthetic pulse to generate the clock signal.

Abstract: Methods and systems for providing a low-rate data signal. Received input data bits are Manchester modulated onto successive multicarrier symbols in the time domain. Each multicarrier symbol includes orthogonal sub-carrier and a null sub-carrier. A stored waveform can be retrieved to code the sub-carriers. The successive multicarrier symbols are up-converted to a carrier frequency to provide the low-rate data signal, and the low-rate data signal is transmitted.

Abstract: The present disclosure discloses a data transmission method, a transmit end device, and a receive end device. The method includes performing bit mapping processing on a first part of bits of a first data bit group, to generate a first modulation symbol and determining a first precoding matrix from multiple preset precoding matrices according to a second part of bits of the first data bit group. The method also includes performing precoding processing on the first modulation symbol according to the first precoding matrix, to obtain a first modulation symbol matrix and transmitting the first modulation symbol matrix to a receive end device by using at least two antennas.

Abstract: A method and apparatus for receiving broadcast signals are discussed. The method includes receiving the broadcast signals; demodulating the received broadcast signals by an Orthogonal Frequency Division Multiplex (OFDM) scheme; obtaining broadcast data from a signal frame in the demodulated broadcast signals, wherein the broadcast data includes video data or audio data, and the broadcast data is carried by only a Data Pipe (DP); decoding the broadcast data; and output-processing the decoded broadcast data to output a data packet, wherein the data packet includes a Transport Stream (TS) packet, wherein a header of the data packet includes first information indicating whether a header deletion is performed in the TS packet, wherein the header of the data packet further includes second information indicating whether a null packet deletion is performed, and wherein when the second information is not a zero value, the null packet is deleted prior to the data packet.

Abstract: Embodiments of the present disclosure provide a method for signal compensation, including: receiving, by a receiver via N receiving antennas, a plurality of channel estimation preamble signals sent by M transmitting antennas of a remote transmitter; determining, by the receiver, channel estimation parameters according to the first pilot signals of the M transmitting antennas contained in the plurality of channel estimation preamble signals; receiving, by the receiver, data signals and second pilot signals sent on a first data symbol by the M transmitting antennas; determining, by the receiver, channel phase shift parameters according to signals arrived at the N receiving antennas which come from the second pilot signals; and determining, by the receiver according to the channel estimation parameters and the channel phase shift parameters, signal compensation for the data signals arrived at the N receiving antennas. Accuracy of demodulation for transmitted data to a certain extent is improved.

Abstract: A semiconductor device (10) includes a transmitting circuit (12) that converts transmission data into a transmission signal with a specified frequency, an amplifier (13) that amplifies a power of the transmission signal, a matching circuit (14) that converts the transmission signal from a balanced signal to an unbalanced signal, and a filter circuit (14) that restricts a frequency band of the transmission signal. The matching circuit includes a primary inductor and a secondary inductor, the filter circuit includes an inductor for a filter, and the primary inductor, the secondary indictor and the inductor for a filter are wound substantially concentrically on one plane.

Abstract: Embodiments are generally directed to signal phase optimization in memory interface training. An embodiment of an apparatus includes an interface for at least one signal; and interface training logic capable of automatically adjusting a phase relationship between the signal and a strobe or clock, including establishing a phase delay of the signal and a phase delay of the strobe or clock for training of the interface, wherein the interface training logic is capable of determining a phase delay reduction for the signal subsequent to measurement of an eye margin for the signal, the phase delay reduction to retain a sufficient delay to maintain the eye margin for sampling of the signal.

Abstract: A received signal is enhanced by removing distortion components of a concurrently transmitted signal. A received signal is acquired in a receive frequency band concurrently with transmission of a transmit signal in a transmit frequency band. The received signal includes an intermodulation distortion component of the transmit signal. A representation of the transmit signal is processed using a non-linear predictor to output a distortion signal representing predicted distortion components in the received signal. The received signal is enhanced using the distortion signal by removing the predicted distortion components from the received signal corresponding to the distortion signal.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for autonomous receive (RX) detection. One example method for wireless communications generally includes powering down a portion of a receive path in a first module; detecting, in a second module comprising another portion of the receive path, that a radio frequency (RF) signal has been received by the second module while the portion of the receive path in the first module is powered down; and sending a control signal to power up the portion of the receive path in the first module, based on the detection.

Abstract: A method for selecting an antenna is provided. S1, whether a signal intensity of a default working antenna among multiple antennae of an electronic device is lower than a preset value is detected, when not, repeat S1, otherwise, proceed to S2. S2, whether a current operating environment of the electronic device is matched with a preset operating environment is detected, when yes, proceed to S3, otherwise, proceed to S5. S3, a first antenna of the multiple antennas is enabled as a working antenna, and the first antenna is located on the electronic device at a position that is least affected by the current operating environment. S4, whether a signal intensity of the first antenna is lower than the preset value is detected, when not, repeat S4, otherwise, proceed to S5. S5, an antenna with the highest signal intensity among the multiple antennas is enabled as the working antenna.

Abstract: A wireless communication device includes a first circuit including a baseband circuit and a radio circuit, and at least one frontend module (FEM) remote from the first circuit and placed in close proximity to and coupled to at least one radio-frequency (RF) antenna. The FEM is coupled to the first circuit via interface circuitry. An FEM comprises a frontend (FE) circuit including one or more low-noise amplifiers (LNAs), one or more power amplifiers (PAs), and at least one of a multi-pole switch and a multiplexer. The multi-pole switch and the multiplexer being implemented on a first side of the FEM coupled to the interface circuitry. The interface circuitry includes at least some of filters, splitters, multi-pole switches, and multiplexers to reduce a count of interconnect routes to the at least one FEM.

Abstract: A message-passing decoder operates by storing, at a check node, a minimum value, a next-to-minimum value, an edge location of the minimum value, and information regarding the signs of incoming messages. For an edge which is not the location of a previous minimum value, the minimum value and the next-to-minimum value, and the location of the minimum value, are set based on the magnitude of an incoming message. For an edge which is the location of the previous minimum value, the minimum value and the next-to-minimum value are set based on the magnitude of an incoming message, and when the magnitude of the incoming message is at most equal to the previous next-to-minimum value, the location of the minimum value is set to the respective edge, and when the magnitude of the incoming message is greater than the previous next-to-minimum value, the location of the minimum value is approximated.

Abstract: A transmitting apparatus includes an OFDM modulator that generates a first modulation symbol by modulating a first information signal using a first modulation scheme, a signal point of the first modulated information signal being arranged at a first position in an in-phase quadrature-phase plane and a second modulation symbol by modulating a second information signal using the first modulation scheme, and by changing a second position at which a signal point of the modulated second information signal is arranged to a third position in the in-phase quadrature-phase plane, wherein the third position is different from the first position. An OFDM modulation signal includes the first modulation symbol and the second modulation symbol, wherein the OFDM modulation signal comprises a plurality of subcarriers. A transmitter transmits the OFDM modulation signal.

Abstract: A channel decoding method is provided. The method includes storing, in a memory, a set of first log likelihood ratio (LLR) values corresponding to bits of a codeword generated by modulation of a channel-encoded signal; changing, into a preset value, at least one LLR value corresponding to previously defined bits of the codeword from among the set of the first LLR values, to generate a set of second LLR values; and performing forward error correction (FEC) based on the set of the second LLR values and an FEC code, to estimate the bits of the codeword, in which the FEC code comprises a constraint code for constricting a previously defined structural correlation between the bits of the codeword.

Abstract: Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-

Abstract: A detection system and a detection method for detecting the loss of lock between a PLL reference clock signal and a PLL feedback clock signal. The detection system includes a pseudorandom bit sequence generator; a first shift register; a second shift register; a third shift register; a first synchronizer; a second synchronizer; a third synchronizer; a first comparator; a second comparator; and an alarm control unit. The method comprises the steps of, generating an n-bit wide pseudorandom bit sequence; sampling the sequence with PLL reference clock signal, PLL feedback clock signal and inverse of PLL feedback clock signal; re-sampling and re-synchronizing the sampled sequences; comparing re-sampled and re-synchronized sequence, previously sampled with PLL reference clock signal, with re-sampled and re-synchronized sequences, previously sampled PLL feedback clock signal and inverse of PLL feedback clock signal; generating a flag signal if the comparisons give no match.

Abstract: Embodiments are directed to an apparatus, method and system for relative or absolute equalization of two or more channels. The apparatus includes a receiver that receives a variable-envelope signal, a self-consistent outphasing separator that splits the received variable-envelope signal into constant-envelope signals, and linear pre-equalizers that equalize the constant-envelope signals relative to each other or to some target. The apparatus also includes an analog combiner that combines the constant-envelope signals, and a feedback loop with a processor that receives the combined constant-envelope signals as inputs, analyzes the combined constant-envelope signals to identify pre-equalization inputs that, when applied to the linear pre-equalizers, will equalize the constant-envelope signals, and provide the identified pre-equalization inputs to the linear pre-equalizers, so that the combined constant-envelope signals are equalized relative to each other or to some target.

Abstract: A reflective modulator comprises a coupler, two diodes and two DC block units. The coupler has an input end used to output an output signal, an output end used to output an output signal, a first load end connected to one of the diodes and a second load end connected to another one of the diodes. The DC block units connect between the diodes and the coupler for DC blocking. A message signal is selectively inputted to both of the two DC block units for operating the state of the two diodes. A BPSK modulator using the reflective modulator and a quadrature modulator using the BPSK modulator are also introduced.