Abstract: A continuous-time linear equalizer implementing enhanced analog delay cells with gain-peaking characteristics and a constant delay time. A receiver feed-forward equalizer architecture implements a gain-stage chain, analog multipliers for correcting coefficients, and a linear combiner as an analog summation circuit. Each of the gain stages produces linear gain peaking and presents a constant delay-time (through calibrations) at each stage. Each delay cell includes a transconductance stage configured to convert a differential input voltage signal to a differential output current signal, wherein the transconductance stage includes a differential pair of first and second transistors coupled in a source degeneration configuration, a negative resistance network coupled in parallel with a tunable resistor network, and shunt inductive circuitry coupled in parallel with the negative resistance network.

Abstract: A modulator for generating a control code in response to a frequency control word is provided. The modulator includes an adder, an accumulator, a next state generation unit, and a code generation unit. The adder generates a frequency error signal by calculating a difference between the frequency control word and the control code. The accumulator generates a phase error signal by accumulating the frequency error signal. The phase error signal includes an integer part and a fractional part. The integer part of the phase error signal is a current state signal. The next state generation unit generates a next state signal according to a characteristic probability distribution determined by the fractional part of the phase error signal. The code generation unit generates the control code in response to the current state signal and the next state signal.

Abstract: Embodiments herein describe techniques for synchronizing LFSRs located on two compute devices. To synchronize the LFSRs, a first one of the compute devices may transmit a first training block that includes a predefined bit sequence. The training block is scrambled by a transmitting (TX) LFSR on the first compute device and then transmitted to the second compute device. The second compute device performs an XOR operation to recover the outputs of the TX LFSR that were used to scramble the data. The second compute device can use the outputs of the TX LFSR to determine future outputs of the TX LFSR. These future outputs are then used to initialize a receiving (RX) LFSR on the second compute device. Now, when subsequent training blocks are received, the second compute device can use the initialized RX LFSR to descramble the scrambled training blocks.

Abstract: According to one embodiment of the present invention, a method of transmitting feedback information by a base station supporting multi-user multi-input multi-output (MU-MIMO) to a network entity includes obtaining a projection matrix based on channel information estimated for multiple channels between antennas of the base station and each of user equipments, projecting at least one of the channel information and uplink data received from the user equipments to a second space from a first space using the projection matrix and transmitting feedback information including at least one of the projected channel information and the projected uplink data to the network entity.

Abstract: In a multiple interface, low power and lossy network comprising a plurality of nodes, a low transmission power and medium transmission power topology are defined for the network and a channel-hopping schedule is defined for the devices operating in each topology. A sender determines that data is capable of being transmitted via a link on the low transmission power topology. The sender determines the transmission parameters for the transmission of the data over the link on the low transmission power topology and determines a low transmission power channel for transmission of the data. The sender transmits the determined channel and the transmission parameters to the receiver. The sender transmits the data via the determined channel in the low transmission power topology.

Abstract: According to an embodiment, a reception circuit is configured to receive a reception signal from a transmission circuit through a receiving AC coupling element. The transmission circuit transmits a transmission signal through a transmitting AC coupling element. The receiving AC coupling element is AC coupled to the transmitting AC coupling element. The reception circuit includes a variable gain amplifier, a hysteresis circuit and a first control circuit. The variable gain amplifier is configured to amplify the reception signal with a variable gain to output an amplified signal. The hysteresis circuit has hysteresis in an input/output characteristic, and is configured to output an output signal according to the amplified signal. The first control circuit is configured to control the gain so that an amplitude of the amplified signal approximates a reference amplitude.

Abstract: Embodiments herein describe techniques for synchronizing LFSRs located on two compute devices. To synchronize the LFSRs, a first one of the compute devices may transmit a first training block that includes a predefined bit sequence. The training block is scrambled by a transmitting (TX) LFSR on the first compute device and then transmitted to the second compute device. The second compute device performs an XOR operation to recover the outputs of the TX LFSR that were used to scramble the data. The second compute device can use the outputs of the TX LFSR to determine future outputs of the TX LFSR. These future outputs are then used to initialize a receiving (RX) LFSR on the second compute device. Now, when subsequent training blocks are received, the second compute device can use the initialized RX LFSR to descramble the scrambled training blocks.

Abstract: A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder to encode service data, a mapper to map the encoded service data, a time interleaver to time interleave the mapped service data, wherein the time interleaving is performed depending on number of physical paths for the service data, a frame builder to build at least one signal frame including the time interleaved service data, a modulator to modulate data in the built at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter to transmit the broadcast signals having the modulated data.

Abstract: An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.

Abstract: Described is an apparatus which comprises: an amplifier; a first set of samplers to sample data output from the amplifier according to a clock signal, the set of samplers to generate an output; and a converter to convert the output of the first set of samplers to 1 -hot encoded data.

Abstract: A method of control of a plurality of end-points by a plurality of base stations, comprises issuing a frame by at least one end-point and sending the frame to at least one base station, sending a response frame from the base station to the end-point upon receiving the frame, the response frame comprising a plurality of downchirps, at least two sequences, each comprising a positive acknowledge and an increase rate and a positive acknowledgement and a decrease rate, and additional control sequences.

Abstract: A sensor, a time alignment apparatus, a time processing method, and a time alignment method are provided. The sensor begins to sense at least one sensed data at a first local time instant. The sensor transmits a response message at a second local time instant. The response message carries the at least one sensed data, the first local time instant, and the second local time instant. The time alignment apparatus receives the response message at a first global time instant. The time alignment apparatus calculates a second global time instant that the at least one sensed data being sensed according to a required transmission time between the time alignment apparatus and the sensing apparatus, a clock skew rate between the time alignment apparatus and the sensing apparatus, the first global time instant, the first local time instant, and the second local time instant.

Abstract: A broadcast signal receiver is disclosed. A broadcast signal receiver according to an embodiment of the present invention comprises a constellation mapper for symbol-demapping by using the signaling information as LLR values; a bit deinterleaver for bit multiplexing and block deinterleaving of the signaling information; an FEC decoder for FEC decoding the signaling information; and a descrambler for descrambling the signaling information.

Abstract: In signal processing of the present disclosure, an abnormal correction value as a correction value for correcting a quadrature error that occurs in quadrature modulation is output in malfunction determining processing, and a normal correction value as the correction value is output in calibration processing. The presence or absence of malfunction in the signal processing is determined on the basis of the levels of carrier leak and image leak of the quadrature modulated signal.

Abstract: Spread spectrum clocking circuitry may be configured to produce a spread spectrum clock signal that coordinates the actions of functional circuitry. Spread spectrum clocking circuitry may be configured to include delay circuitry configured to generate a random delay signal based on a random input value and generate the spread spectrum clock signal based on the random delay signal. By introducing true randomness into the delay signal, spread spectrum clocking signal may be able to generate a truly random, as opposed to a merely pseudo random, clock signal.

Abstract: When embedding a signal into a selected subcarrier of a multicarrier downlink waveform of regular data/control signaling, a base station modulates the embedded signal with a different modulation scheme than the other data in the downlink waveform. The base station nulls adjacent subcarriers to minimize interference at a low-power wake-up receiver of an IOE device(s). The IOE device wakes up the low-power wake-up receiver at scheduled times to listen for the signal. For synchronization signals, the IOE device corrects a local clock based on a correlation value of the signal to a predetermined sequence. For wake-up signals, the IOE device correlates whatever is detected at the antenna to a predetermined sequence and compares the correlation value to a predetermined threshold. If the threshold is met, the IOE device registers a wake-up signal and wakes the primary transceiver of the device. If not, the receiver goes back to sleep.

Abstract: A transmitter transmits data using Orthogonal Frequency Division, OFDM, symbols. The transmitter comprising a forward error correction encoder configured to encode the data to form forward error correction encoded frames of encoded data cells, a service frame builder configured to form a service frame for transmission comprising a plurality of forward error correction encoded frames, a convolutional interleaver comprising a plurality of delay portions and configured to convolutionally interleave the data cells of the service frames, a modulation symbol mapper configured to map the interleaved and encoded data cells of the service frames onto modulation cells, and a modulator configured to modulate the sub-carriers of one or more OFDM symbols with the modulation cells.

Abstract: Embodiments herein describe techniques for synchronizing LFSRs located on two compute devices. To synchronize the LFSRs, a first one of the compute devices may transmit a first training block that includes a predefined bit sequence. The training block is scrambled by a transmitting (TX) LFSR on the first compute device and then transmitted to the second compute device. The second compute device performs an XOR operation to recover the outputs of the TX LFSR that were used to scramble the data. The second compute device can use the outputs of the TX LFSR to determine future outputs of the TX LFSR. These future outputs are then used to initialize a receiving (RX) LFSR on the second compute device. Now, when subsequent training blocks are received, the second compute device can use the initialized RX LFSR to descramble the scrambled training blocks.

Abstract: A clock oscillator includes a high speed oscillator generating a high speed clock signal and comprising a digital trimming function; a counter receiving said high speed clock signal at a clock input; a time base having a low drift and controlling said counter, wherein the counter generates a difference between a reference value and a counter value; and a digital integrator receiving said difference value and providing trimming data for said high speed oscillator.

Abstract: Provided is signal processing device including superconducting quantum interference device (SQUID) sensors configured to sense a signal for each of a plurality of channels, analog to digital converters (ADC) configured to convert analog signals input to a predetermined number of channels from the SQUID sensors into digital signals by using a clock signal, local oscillators corresponding to the ADCs, respectively and configured to generate the clock signal having a reference clock frequency for an operation of a corresponding ADC, and a controller configured to the local oscillators to enable the reference clock frequency to have a frequency beyond a frequency range available to the SQUID sensor.