Abstract: There is disclosed a method for producing a silicon single crystal in accordance with the Czochralski method wherein a crystal is pulled with controlling a temperature in a furnace so that &Dgr;G may be 0 or a negative value, where &Dgr;G is a difference between the temperature gradient Gc (° C./mm) at the center of a crystal and the temperature gradient Ge (° C./mm) at the circumferential portion of the crystal, namely &Dgr;G=(Ge−Gc), wherein G is a temperature gradient in the vicinity of a solid-liquid interface of a crystal from the melting point of silicon to 1400° C.

Abstract: A method and system for processing a substrate in the presence of high purity C.sub.5 F.sub.8. When processing oxides and dielectrics in a gas plasma processing system, C.sub.5 F.sub.8 is used in combination with a carrier gas (e.g., Ar) and one or more of CO and O.sub.2. When using a silicon nitride (Si.sub.x N.sub.y) layer as an etch stop, effective etching is performed due to the selectivity of oxides versus silicon nitride. The method is used when etching down to self-aligning contacts and other layers. The method may be practiced with or without using an anti-reflective coating underneath the photoresist layer.

Abstract: A method of removing microscratches in planarized dielectric surfaces covering conductor layers in submicron integrated circuit structures includes a semiconductor substrate having at least one dielectric layer formed thereon followed by a chemical mechanical polishing process for planarization. The removal of microscratches includes depositing a PE-CVD polymer layer to fill the microscratches, caused by CMP planarization, and to cover the planarized dielectric surface with a thin layer of the polymer. Deposition is followed by introducing an etching gas into the CVD chamber for an etch back of the just deposited polymer to well below the depth of the microscratches wherein the deposited polymer has the same etch rate as the dielectric layer formed thereunder.

Abstract: There is disclosed a method of manufacturing a silicon monocrystal in accordance with the Czochralski method in which a seed crystal is brought into contact with silicon melt and is then slowly pulled while being rotated in order to grow a silicon monocrystalline ingot below the seed crystal. In the method, there is used a seed crystal whose a tip end to be brought into contact with the silicon melt has a sharp-pointed shape or a truncation thereof. The tip end of the seed crystal is gently brought into contact with the silicon melt, and the seed crystal is then lowered at a low speed in order to melt the tip end portion of the seed crystal until the thickness of the tip portion increases to a desired value. Subsequently, the seed crystal is pulled slowly in order to grow a silicon monocrystalline ingot having a desired diameter without performance of a necking operation. During the growth of the silicon monocrystalline ingot, a part of the crystal is mechanically held.

Abstract: A method of fabricating an unlanded metal via of multi-level interconnection. The method is characterized by utilizing damascene scheme to form a metal wiring layer so that the processes are simplified. Moreover, by this method of the invention, a problem of difficulty in filling dielectric material between the metal wiring lines can be avoided and the metal layer does not have to be etched prior to filling the dielectric material. Further more, an etching stop layer is formed over the first inter-metal dielectric layer to avoid overetching during the formation of metal via, which therefore avoid short circuit. Forming the metal wiring lines by damascene scheme allows the etching stop layer to be easily formed over the first dielectric layer, without over etching the metal via.