Abstract: A wafer-scale integrated circuit has a plurality of data-processing cells disposed on a semiconductor wafer together with a port for providing communications with a controller. A branched spiral of inter-coupled working cells is grown starting at the port by testing cells and incorporating them into the branched spiral if found to be working, otherwise selecting alternative cells for testing. The growth of the branched spiral is such as to allow for the incorporation of cells trapped in cul-de-sacs. Each cell is operable to receive a unique cell name from the controller and is thereafter operable to respond to commands from the controller bearing its unique cell name to couple firstly to one neighbor and secondly, at any time thereafter, to couple to a further neighboring cell. The controller is provided with means for maintaining records of successful interconnections for later use.

Abstract: An interrupt processor is disclosed for an instruction pipelined digital processor, which includes an instruction classification system with a logic class decoder, a multistage, pipelined, interruptible-sequence detector, a multistage variable-return-address generator, and an active instruction completion, suppression, and termination control, to enable interrupting a sequence of instructions which execute out-of-order in the pipelined and digital processor, and to enable allowing a subsequent return to the interrupted program to resume processing of that program without error.