Abstract: A method and apparatus for determining and verifying user data are provided. One or more facts about the user of a client system such as an internet terminal are maintained in a set of information fields, each information field is associated with a status field for indicating a level of certainty regarding the accuracy of the information contained in the corresponding information field. It is determined whether or not a source of data exists that is more reliable than the currently stored information. If a more reliable source of data is determined to exist, then information is retrieved from the more reliable source of data and the current information is replaced with the retrieved information. According to another aspect of the present invention the accuracy of facts gathered about a user of a client system are evaluated by monitoring online activity of the user. For example, information transmitted between a server system and the client system may be observed.

Abstract: A device and method to control a node within a network is disclosed. The node can have any number of ports N where N is an integer greater than one. The device has N-port modules, corresponding to the number of ports in the node, each port module associated with one port for controlling reception and transmission of information through the associated port. The port modules are substantially identical and the device can be manufactured by replicating N-port modules, one port module for each port. The port modules have a priority within the node. The priority can be created by connecting the port modules in a daisy chain configuration. The port module having the highest priority compares the unique identifier of the node with the unique identifier being received by the port associated with the highest priority port module. The results of this comparison are sent to the next highest priority port module.

Abstract: A processor according to the present invention includes a user-accessible 1 bit register for indicating, upon instruction breaking or data breaking occurring, whether any instruction or data to be debugged is existent in a cache memory or in a memory, and the 1 bit register possesses a bit issued correspondingly to a hit signal issued from the cache memory, whereby it can be known with each whether the instruction or data is existent in the cache memory or in the memory.

Abstract: A cache control maintains a history table SETLAT for the prediction of line entry (i.e., set member) within a congruence class for cache accessing. For a given cache access, a SETLAT entry can be selected based on the requesting logical address bits directly. The selection of a SETLAT entry may also be based on the hashing of such logical address bits together with other information in order to achieve sufficient randomization. A similar hashing history table may be devised to predict virtual address translation information with high accuracy. Such prediction mechanisms not only allow efficient implementation of the cache access path but also offer the opportunity of achieving multiple accesses per cycle.The proposed prediction method also provides a generic approach to efficient implementations for various directory based table accesses.

Abstract: A method and apparatus for monitoring transactions on a system bus for invalidate requests, including a queue for storing the invalidate requests which is divided into two parts. The first part of the queue is contained within a cache controller to ensure that an invalidate request is immediately available for processing when the cache controller is otherwise idle. The second part of the queue is contained within a system interface to ensure that the system interface can detect and respond to more system transactions before the first invalidate request has been processed and to enable the system interface to be immediately aware if the entire queue is full.