Patents Examined by Gareth G. Shaw
  • Patent number: 4931931
    Abstract: In a method for processing logic programs--especially in Prolog-like languages--using at least one processor, which allows parallelism--also retroactively--by an existing process, called "father", creating at optional OR-parallel nodes at least one process, called "son", standing in an OR-parallel relationship to the father, a deep-binding list, called "hash-window" is created only for the newly created son in which--while processing the split-off OR-parallel branch--it performs bindings to variables commonly accessible to it and its father, called "commonly accessible variables.
    Type: Grant
    Filed: July 2, 1987
    Date of Patent: June 5, 1990
    Assignee: European Computer-Industry Research Centre GmbH
    Inventors: Jean-Claude Syre, Harald Westphal, Max Hailperin