Patents Examined by Gary J. Portka
  • Patent number: 11334258
    Abstract: A new approach is proposed to support hardware-based memory region protection for an electronic device. One or more sources/requesting access to a memory/storage that is local to or associated with the electronic device are categorized into at least two types—a set of trusted sources and a set of untrusted sources. Accordingly, a memory manager is configured to partition the memory into a plurality of regions including at least a secure region that is accessible only by a trusted source and a non-secure region that is accessible by an untrusted source. Any access attempt to the secure region by one of the untrusted sources will be blocked. During operation, the memory manager is configured to dynamically adjust the demarcation and/or size of the secure region and the non-secure region of the memory via remapping of the memory based on current access need to data maintained in the memory.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: May 17, 2022
    Assignee: Marvell Asia Pte Ltd
    Inventors: Ramacharan Sundararaman, Nithyananda Miyar, Hakseon Lee
  • Patent number: 11334269
    Abstract: Storage pools having categorized archival storage tapes according to content of files stored on each tape. Archiving new files into the storage pools according to content of the new files for efficient retrieval of files from storage tapes organized by category of content. Recall of multiple files from archival storage tapes to primary storage of an hierarchical storage management system is efficiently performed such that tape mounting operations are minimized.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: May 17, 2022
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Hiroaki Kikuchi, Takuya Goto, Asako Ono, Xiangning Liu
  • Patent number: 11327666
    Abstract: A subset of drives with protection groups that have D data members and P parity members is scaled in single drive increments. A plurality of indexed partitions equal in size and number are created on (D+P) indexed drives. Protection groups that have D data members and P parity members are created on individual partition indexes of the (D+P) drives. When a new drive is added some of the protection group members located on the (D+P) drives are selected using modulo arithmetic. The selected protection group members are relocated to the new drive and new protection groups are created using the partitions made available due to the relocations. When (D+P) new drives have been added the drive subset may be split into two drive subsets. The modulo arithmetic may include selecting the members of protection group X that are on partition X of drive Y that satisfy the condition (X?Y+N?1) modulo W=0, where N is a count of new drives added to the (D+P) drives and W=(D+P).
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: May 10, 2022
    Assignee: Dell Products L.P.
    Inventor: Kuolin Hua
  • Patent number: 11327654
    Abstract: A method for a baseboard management controller mounting a folder with KVM includes following steps. A first size of a to-be-mounted folder is calculated. A second size of a mirror image file corresponding to the to-be-mounted folder is calculated based on the first size. A default storage path is allocated for the mirror image file, and it is obtained a remaining storage capacity of a disk where the default storage path is located. If the remaining storage capacity is less than the second size, a prompt dialog box, for selecting a user storage path for the mirror image file, is displayed to the user. If the remaining storage capacity of the disk where the default storage path or the user storage path is located is greater than the second size, the to-be-mounted folder is mounted to a server.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: May 10, 2022
    Assignee: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY CO., LTD.
    Inventor: Xuelong Wang
  • Patent number: 11314427
    Abstract: Methods, systems, and devices for memory device with enhanced data reliability capabilities are described. For a write operation, a memory device may receive a write command from a host device indicating a first set of data. The memory device may determine to operate in first mode of operation associated with a reliability above a threshold and generate a second set of data to store with the first set of data based on operating in the first mode of operation. For a read operation, the memory device may identify that a read command received from a host device is associated with the first mode of operation. Based on operating in the first mode of operation, the memory device may select one or more reference thresholds (e.g., a subset of reference thresholds) to retrieve the first set of data and transmit the first set of data to the host device.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: April 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Deping He, David Aaron Palmer
  • Patent number: 11307777
    Abstract: Embodiments of the disclosure relate to a memory system and an operating method thereof. The memory system may decrypt first firmware which is stored in the memory device and is encrypted using a symmetric-key encryption algorithm, with a first key stored in the memory device, may generate a second key based on second firmware, which is obtained by decrypting the first firmware, first data stored in a first area in the memory controller, and second data stored in a second area in the memory device, and may drive the second firmware when the first key and the second key are the same.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventors: Sung Jin Park, Jung Ae Kim
  • Patent number: 11294581
    Abstract: A computer system 100 that allows a storage facility 500 to be shared by multiple different users of an Infrastructure as a Services (IaaS) system while maintaining security separation between the users is provided. A controller 150 configured for use in the computer system and a corresponding method and computer program are also provided. The computer system 100 comprises a logic block 101 that comprises one or more processing units that execute instructions, the logic block 101 configured to issue requests to read from and write to storage over a first interface 102; and a controller 150 that is configured to implement a communications link to storage 500; implement a communications link 300 to a second computer system 200 and to receive information identifying a current user of the logic block 101 from the second computer system 200; and receive the requests to read from and write to storage from the logic block 101 over the first interface 102, and to complete the requests.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: April 5, 2022
    Assignee: GARRISON TECHNOLOGY LTD.
    Inventors: Henry Harrison, David Garfield
  • Patent number: 11287974
    Abstract: The present invention provides systems and methods for data storage. A hierarchical storage management architecture is presented to facilitate data management. The disclosed system provides methods for evaluating the state of stored data relative to enterprise needs by using weighted parameters that may be user defined. Also disclosed are systems and methods evaluating costing and risk management associated with stored data.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: March 29, 2022
    Assignee: Commvault Systems, Inc.
    Inventors: Anand Prahlad, Srinivas Kavuri, Andre Duque Madeira, Norman R. Lunde, Alan G. Bunte, Andreas May, Jeremy Alan Schwartz
  • Patent number: 11281575
    Abstract: A system is provided to receive a request to write a sector of data to a non-volatile storage device, wherein the request is associated with a physical address in the non-volatile storage device at which the sector of data is to be written. The system identifies, based on the physical address, a channel buffer to which the sector of data is to be transmitted, and stores the sector of data in the channel buffer. Responsive to determining that the channel buffer stores other sectors, the system writes the sector of data and the other sectors of data to the non-volatile storage device based on the physical address.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: March 22, 2022
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 11275524
    Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method of a memory system. According to embodiments of the present disclosure, the memory system may transmit, to a host, target data, and, upon receiving, from the host, information indicating that at least one bit-flip has occurred in the target data, may perform an error handling operation on the at least one bit-flip in the target data. Accordingly, the memory system is able to reduce resource used in checking the bit-flip and to alleviate the constraints of the algorithms used in checking for the bit-flip.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: March 15, 2022
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 11262941
    Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. An example method includes receiving a data clock signal responsive to receiving a timing command, performing an access operation responsive to receiving an access command associated with the timing command, providing an access data clock signal based on the data clock signal, and providing an access data clock signal based on the data clock signal. The access command may be separated in time from the associated timing command by at least one clock cycle of a system clock signal. In some examples, the access command may precede the associated timing command or may follow the associated timing command. In some examples, the access command may immediately follow or precede the associated timing command.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kang-Yong Kim, Hyun Yoo Lee, John D. Porter
  • Patent number: 11256419
    Abstract: The deterioration of the operational efficiency of an optimal object placement device caused by the degradation in the access speed to the objects is inhibited. An optimal object placement device optimizes, in an information processing system having a storage area in each of a plurality of sites and in which a user can access objects stored in the storage area of all of the sites from each of the sites, placement of each of the objects; and an optimal object placement method is executed by the optimal object placement device, wherein control is executed for detecting an access tendency of the user's access to the objects.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: February 22, 2022
    Assignee: HITACHI, LTD.
    Inventors: Takashi Miyawaki, Yuta Nishihara, Atsushi Sera
  • Patent number: 11249893
    Abstract: A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: February 15, 2022
    Assignee: SILICON MOTION INC.
    Inventor: Chao-Kuei Hsieh
  • Patent number: 11243702
    Abstract: In some aspects, devices, systems, and methods are provided that relate to data deduplication performed in data storage devices, such as solid-state drives (SSD) or drives of any other type. In some aspects, devices, systems, and methods are provided that relate to hierarchical data deduplication at a local and system level, such as in a storage system built with one or more SSDs having built-in data deduplication functionality. The hierarchical data deduplication utilizes the IDs in the data storage devices to decide if the incoming data has to be stored or if a copy of the incoming data is already stored. In hierarchical data deduplication, no IDs (or signatures) are required to be stored at a system level. In some aspects, data steering is provided that enables data storing coordination in a system that consists of a set of data storage device (e.g., SSDs) having built-in data deduplication.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: February 8, 2022
    Assignee: SMART IOPS, INC.
    Inventors: Manuel Antonio d'Abreu, Ashutosh Kumar Das
  • Patent number: 11226749
    Abstract: Apparatus and methods managing and controlling access to data are disclosed. An example method for managing data in a computer system includes: a processor effecting storage of first subsidiary data in the data storage device, the first subsidiary data representing information related to a customer account; the processor effecting storing of second subsidiary data in the data storage device, the second subsidiary data representing at least a portion of the information related to the customer account; the processor effecting a determination of a geographic location of a computing device that is remote to the computer system; and, in response to the processor determining that the geographic location of the computing device meets a predefined criterion, the processor effecting a change to the first subsidiary data and a related change to the second subsidiary data.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: January 18, 2022
    Assignee: POINTSBET PTY LTD.
    Inventor: Manjit Gombra Singh
  • Patent number: 11216201
    Abstract: Techniques for performing data movements may include tracking sets of I/O statistics for a extents, wherein each of the sets of I/O statistics characterizes I/O operations directed to a corresponding one of the extents having data stored on a first storage tier of first non-volatile storage devices; determining, in accordance with the sets of I/O statistics, a list that includes one or more of the extents qualified for promotion from the first storage tier to a second storage tier, wherein the second storage tier includes second non-volatile storage devices have a higher performance ranking that the first non-volatile storage devices of the first storage tier; selecting, from the list, a first extent to be promoted from the first storage tier to the second storage tier; and performing first processing that promotes only cached data of the first extent from the first storage tier to the second storage tier.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: January 4, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Owen Martin, Vladimir Desyatov, Mark D. Moreau, Dustin H. Zentz, Anoop Raghunathan, Sean B. Reilly
  • Patent number: 11216198
    Abstract: A technique involves: in response to receiving a first request for adjusting a first width of a disk array to a second width, obtaining, based on source identification information of a source stripe group in the disk array in the first request, source block identification information of a source block associated with the source stripe group. The technique further involves: determining destination identification information of a destination stripe group associated with the second width for storing data. The technique further involves: storing, based on the source identification information and the destination identification information, source data and metadata for the source data from the source block into a destination block of the destination stripe group, the metadata including node identification information for accessing nodes of the source block. The technique further involves: adjusting the node to access the destination block based on the node identification information.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: January 4, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Jian Gao, Shaoqin Gong, Lifeng Yang, Xinlei Xu, Xiongcheng Li
  • Patent number: 11210018
    Abstract: Method, apparatus and computer program product for linking data entries across data sources. For example, the apparatus includes at least one processor and at least one non-transitory memory including program code. The at least one non-transitory memory and the program code are configured to, with the at least one processor, store unlinked data entries in a staging memory area; store linked data entries in an active memory area; identifying a linked state status for the staging memory area, wherein the linked state status initially indicates a non-linked state; repeatedly performing one or more cross-data-source linking operations until the linked state status for the staging memory area indicates a linked state; and in response to determining that the linked state status for the staging memory area indicates the linked state, linking the multiple data entries by merging the staging memory area and the active memory area to generate linked data.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: December 28, 2021
    Assignee: Honeywell International Inc.
    Inventors: Miroslav Krasimirov Kramolinski, Ivan Valeriev Markov, Hristo Tihomirov Kyurkchiev
  • Patent number: 11200162
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller, random-access memory (RAM), and a NVM unit, where in the NVM unit comprises a plurality of zones. The RAM unit comprises a logical to physical address (L2P) table for the plurality of zones. The L2P table comprises pointers that are associated with a logical block address (LBA) and the physical location of the data stored in the NVM. The L2P table comprises one pointer per erase block or zone. When a command is received to read data within the NVM, the controller reads the L2P table to determine the LBA and associated pointer of the data. The controller can then determine which zone or erase block the data is stored in, and calculates various offsets of wordlines, pages, and page addresses to find the exact location of the data in the NVM.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: December 14, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel L. Helmick, Liam Parker, Alan D. Bennett, Horst-Christoph Georg Hellwig
  • Patent number: 11194485
    Abstract: Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry 8. In response to a realm switch from a source realm to a target realm at a more privileged exception level, state masking of a subset of architectural state associated with a source realm is performed to make the state inaccessible to a target realm. In response to a flush command following the realm switch, any of the subset of architectural state data not already saved to at least one realm execution context memory region is ensured to be saved.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: December 7, 2021
    Assignee: ARM LIMITED
    Inventors: Jason Parker, Matthew Lucien Evans, Gareth Rhys Stockwell, Djordje Kovacevic